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2013-04-19Revert "PR14606: debug info imported_module support"Eric Christopher
This reverts commit r179836 as it seems to have caused test failures. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179840 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19PR14606: debug info imported_module supportDavid Blaikie
Adding another CU-wide list, in this case of imported_modules (since they should be relatively rare, it seemed better to add a list where each element had a "context" value, rather than add a (usually empty) list to every scope). This takes care of DW_TAG_imported_module, but to fully address PR14606 we'll need to expand this to cover DW_TAG_imported_declaration too. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179836 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19R600: Add pattern for the BFI_INT instructionTom Stellard
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179830 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19R600: Reorganize lit tests and document how they should be organizedTom Stellard
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179828 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18Disable PPC comparison optimization by defaultHal Finkel
This seems to cause a stage-2 LLVM compile failure (by crashing TableGen); do I'm disabling this for now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179807 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18Implement optimizeCompareInstr for PPCHal Finkel
Many PPC instructions have a so-called 'record form' which stores to a specific condition register the result of comparing the result of the instruction with zero (always as a signed comparison). For integer operations on PPC64, this is always a 64-bit comparison. This implementation is derived from the implementation in the ARM backend; there are some differences because PPC condition registers are allocatable virtual registers (although the record forms always use a specific one), and we look for a matching subtraction instruction after the compare (but before the first use) in addition to before it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179802 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18X86: Add an SSE2 lowering for 64 bit compares when pcmpgtq (SSE4.2) isn't ↵Benjamin Kramer
available. This pattern started popping up in vectorized min/max reductions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179797 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18Allow misaligned stores in x86 fast-isel.Derek Schuff
In X86FastISel::X86SelectStore(), improperly aligned stores are rejected and handled by the DAG-based ISel. However, X86FastISel::X86SelectLoad() makes no such requirement. There doesn't appear to be an x86 architectural correctness issue with allowing potentially unaligned store instructions. This patch removes this restriction. Patch by Jim Stichnot. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179774 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18Fix for PR14824, An ARM Load/Store Optimization bugHao Liu
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179751 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-17This patch teaches x86 fast-isel to generate the native div/idiv instructionsEli Bendersky
for the sdiv/srem/udiv/urem bitcode instructions. This is done for the i8, i16, and i32 types, as well as i64 for the x86_64 target. Patch by Jim Stichnoth git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179715 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-17R600: Make Export Instruction not duplicableVincent Lejeune
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179686 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-16Add support for the div/rem instructions under x86 fast-isel.Jim Stichnoth
BUG= https://code.google.com/p/nativeclient/issues/detail?id=3385 Review URL: https://codereview.chromium.org/14261012
2013-04-16[XCore] Extend test to check positve offsets are folded into addresses.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179621 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-16[XCore] Give test more generic name.Richard Osborne
I intend to extend the test with more offset folding checks git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179620 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-16[XCore] Convert a couple of tests to FileCheck.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179619 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-16Implement ARM unwind opcode assembler.Logan Chien
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179591 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-16Add 64-bit multiply and divide instructions for SPARC v9.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179582 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15R600/SI: Emit config values in register value pairs.Tom Stellard
Instead of emitting config values in a predefined order, the code emitter will now emit a 32-bit register index followed by the 32-bit config value. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179546 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15R600/SI: Emit configuration value in the .AMDGPU.config ELF sectionTom Stellard
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179545 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15R600: Emit ELF formatted code rather than raw ISA.Tom Stellard
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179544 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15Avoid outputting temporary test file into source tree.Tim Northover
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179532 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15Fix PPC64 CR spill location for callee-saved registersHal Finkel
This fixes an ABI bug for non-Darwin PPC64. For the callee-saved condition registers, the spill location is specified relative to the stack pointer (SP + 8). However, this is not relative to the SP after the new stack frame is established, but instead relative to the caller's stack pointer (it is stored into the linkage area of the parent's stack frame). So, like with the link register, we don't directly spill the CRs with other callee-saved registers, but just mark them to be spilled during prologue generation. In practice, this reverts r179457 for PPC64 (but leaves it in place for PPC32). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179500 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-14Use i32 for all SPARC shift amounts, even in 64-bit mode.Jakob Stoklund Olesen
Test case by llvm-stress. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179477 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-14Add support for the abs64 SPARC v9 code model.Jakob Stoklund Olesen
For when 16 TB just isn't enough. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179474 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-14Add support for the SPARC v9 abs44 code model.Jakob Stoklund Olesen
This is the default model for non-PIC 64-bit code. It supports text+data+bss linked anywhere in the low 16 TB of the address space. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179473 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-14Also put target flags on SPARC constant pool references.Jakob Stoklund Olesen
Constant pool entries are accessed exactly the same way as global variables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179471 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-14Fix patterns for 64-bit pointers.Jakob Stoklund Olesen
This fixes the pic32 code model for SPARC v9. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179469 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-13Define SPARC code models.Jakob Stoklund Olesen
Currently, only abs32 and pic32 are implemented. Add a test case for abs32 with 64-bit code. 64-bit PIC code is currently broken. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179463 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-13Spill and restore PPC CR registers using the FP when we have oneHal Finkel
For functions that need to spill CRs, and have dynamic stack allocations, the value of the SP during the restore is not what it was during the save, and so we need to use the FP in these cases (as for all of the other spills and restores, but the CR restore has a special code path because its reserved slot, like the link register, is specified directly relative to the adjusted SP). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179457 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-13Further generalize this scheduler test.Andrew Trick
The order of copies depends on queue order, which is not very stable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179456 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-13Fix a dislexic regex.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179455 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-13Add a missing REQUIRES: assertsAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179453 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-13MI-Sched: schedule physreg copies.Andrew Trick
The register allocator expects minimal physreg live ranges. Schedule physreg copies accordingly. This is slightly tricky when they occur in the middle of the scheduling region. For now, this is handled by rescheduling the copy when its associated instruction is scheduled. Eventually we may instead bundle them, but only if we can preserve the bundles as parallel copies during regalloc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179449 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-13[mips] Reapply r179420 and r179421.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179434 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-12Revert r179420 and r179421.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179422 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-12[mips] Instruction selection patterns for carry-setting and using addAkira Hatanaka
instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179421 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-12[mips] v4i8 and v2i16 add, sub and mul instruction selection patterns.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179420 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-12Replace coff-/elf-dump with llvm-readobjNico Rieck
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179361 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-12Fix the test on linux by setting the triple and the align formatNadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179354 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-12Add a flag to align all basic blocks in the function.Nadav Rotem
When debugging performance regressions we often ask ourselves if the regression that we see is due to poor isel/sched/ra or due to some micro-architetural problem. When comparing two code sequences one good way to rule out front-end bottlenecks (and other the issues) is to force code alignment. This pass adds a flag that forces the alignment of all of the basic blocks in the program. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179353 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-11Use FileCheck instead of grep.Preston Gurd
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179322 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-11Mips specific inline asm memory operand modifier test caseJack Carter
These changes are based on commit responses for r179135. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179315 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-11Add a CHECK-NOT for a more faithful translation of the original grep | count 2.Eli Bendersky
Thanks to Reid Kleckner for catching this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179289 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-11Add missing colons to check lines.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179277 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-11FileCheckize a bunch of tests.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179276 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-11Optimize vector select from all 0s or all 1sMichael Liao
As packed comparisons in AVX/SSE produce all 0s or all 1s in each SIMD lane, vector select could be simplified to AND/OR or removed if one or both values being selected is all 0s or all 1s. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179267 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-11Enhance bool simplifcation in X86 to handle more casesMichael Liao
This patch is revised based on patch from Victor Umansky <victor.umansky@intel.com>. More cases are handled in X86's bool simplification, i.e. - SETCC_CARRY - value is truncated to i1 with AND As a by-product, PR5443 is also fixed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179265 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10Rewrite some of the test/CodeGen/X86 tests to use FileCheck instead of grepEli Bendersky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179241 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10Manually remove successors in if conversion when CopyAndPredicateBlock is usedHal Finkel
In the simple and triangle if-conversion cases, when CopyAndPredicateBlock is used because the to-be-predicated block has other predecessors, we need to explicitly remove the old copied block from the successors list. Normally if conversion relies on TII->AnalyzeBranch combined with BB->CorrectExtraCFGEdges to cleanup the successors list, but if the predicated block contained an un-analyzable branch (such as a now-predicated return), then this will fail. These extra successors were causing a problem on PPC because it was causing later passes (such as PPCEarlyReturm) to leave dead return-only basic blocks in the code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179227 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10Mips specific inline asm memory operand modifier test caseJack Carter
These changes are based on commit responses for r179135. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179225 91177308-0d34-0410-b5e6-96231b3b80d8
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