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2012-06-04Add a test case for mips64 unaligned load/store instructions.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157939 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-04Rename test/CodeGen/Mips/load-shift-left-right.ll.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157938 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-04Implement local-exec TLS on PowerPC.Roman Divacky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157935 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-04Remove the "-promote-elements" flag. This flag is now enabled by default.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157925 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-04Enable generating PPC pre-increment (r+imm) instructions by default.Hal Finkel
It seems that this no longer causes test suite failures on PPC64 (after r157159), and often gives a performance benefit, so it can be enabled by default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157911 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-03Rename FMA3 feature flag to just FMA to match gcc so it can be added to clang.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157903 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-03Rename fma4 intrinsics to just fma since they are now used for both FMA4 and ↵Craig Topper
FMA3. Autoupgrade support coming in a separate commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157898 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-03Revert r157831Manman Ren
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157896 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-03Use sse_load_f32/64 for scalar FMA3 intrinsic patterns instead of 128-bit ↵Craig Topper
loads to match instruction behavior. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157895 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-02ARM: add testing case for struct byvalManman Ren
rdar://9877866 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157876 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-02Add another test case which tests Mips' unaligned load/store instructions.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157874 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-02Fix test cases in test/CodeGen/Mips.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157868 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-01X86: peephole optimization to remove cmp instructionManman Ren
This patch will optimize the following: sub r1, r3 cmp r3, r1 or cmp r1, r3 bge L1 TO sub r1, r3 bge L1 or ble L1 If the branch instruction can use flag from "sub", then we can eliminate the "cmp" instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157831 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-01testcase for PR13006, thanks to Duncan for filing it.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157824 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-01Implement the local-dynamic TLS model for x86 (PR3985)Hans Wennborg
This implements codegen support for accesses to thread-local variables using the local-dynamic model, and adds a clean-up pass so that the base address for the TLS block can be re-used between local-dynamic access on an execution path. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157818 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-01Remove fadd(fmul) patterns for FMA3. This needs to be implemented by paying ↵Craig Topper
attention to FP_CONTRACT and matching @llvm.fma which is not available yet. This will allow us to enablle intrinsic use at least though. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157804 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-01enhance the logic for looking through tailcalls to look through transparent ↵Chris Lattner
casts in multiple-return value scenarios, like what happens on X86-64 when returning small structs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157800 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-01enhance getNoopInput to know about vector<->vector bitcasts of legalChris Lattner
types, as well as int<->ptr casts. This allows us to tailcall functions with some trivial casts between the call and return (i.e. because the return types disagree). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157798 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-01add some simple 64-bit tail call tests.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157797 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-01merge some tests.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157795 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-01rename testChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157794 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-31Make this testcase independent of register allocation.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157761 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-31X86: replace SUB with CMP if possibleManman Ren
This patch will optimize the following movq %rdi, %rax subq %rsi, %rax cmovsq %rsi, %rdi movq %rdi, %rax to cmpq %rsi, %rdi cmovsq %rsi, %rdi movq %rdi, %rax Perform this optimization if the actual result of SUB is not used. rdar: 11540023 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157755 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-31Added FMA3 Intel instructions.Elena Demikhovsky
I disabled FMA3 autodetection, since the result may differ from expected for some benchmarks. I added tests for GodeGen and intrinsics. I did not change llvm.fma.f32/64 - it may be done later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157737 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-31Add intrinsic for pclmulqdq instruction.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157731 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-30Prioritize smaller register classes for urgent evictions.Jakob Stoklund Olesen
It helps compile exotic inline asm. In the test case, normal GR32 virtual registers use up eax-edx so the final GR32_ABCD live range has no registers left. Since all the live ranges were tiny, we had no way of prioritizing the smaller register class. This patch allows tiny unspillable live ranges to be evicted by tiny unspillable live ranges from a smaller register class. <rdar://problem/11542429> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157715 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-30Add support for the mips inline asm 'm' output modifier.Eric Christopher
Patch by Jack Carter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157709 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-30Switch the canonical FMA term operand order to match both the comment I ↵Owen Anderson
wrote and the usual LLVM convention. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157708 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-30Teach DAGCombine to canonicalize the position of a constant in the term ↵Owen Anderson
operands of an FMA node. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157707 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-30it's pointed out that R11 can be used for magic things, and doing things ↵Chris Lattner
just for 64-bit registers is silly. Just optimize 3 more. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157699 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-30Extend the (abi-irrelevant) return convention to be able to return more than ↵Chris Lattner
two values in integer registers. This is already supported by the fastcc convention, but it doesn't hurt to support it in the standard conventions as well. In cases where we can cheat at the calling convention, this allows us to avoid returning things through memory in more cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157698 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-30[arm-fast-isel] Add support for the llvm.frameaddress() intrinsic.Chad Rosier
Patch by Jush Lu <jush.msn@gmail.com>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157696 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-30Teach taildup to update livein set. rdar://11538365Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157663 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-30Add an insertPass API to TargetPassConfig. <rdar://problem/11498613>Bob Wilson
Besides adding the new insertPass function, this patch uses it to enhance the existing -print-machineinstrs so that the MachineInstrs after a specific pass can be printed. Patch by Bin Zeng! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157655 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-29Add intrinsics, code gen, assembler and disassembler support for the SSE4a ↵Benjamin Kramer
extrq and insertq instructions. This required light surgery on the assembler and disassembler because the instructions use an uncommon encoding. They are the only two instructions in x86 that use register operands and two immediates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157634 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-28Add llvm.fabs intrinsic.Peter Collingbourne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157594 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-27These tests used intrinsics with the wrong prototype. They weren't caught ↵Chris Lattner
because the old verifier just checked that something "was a pointer", but not that the pointee was correct. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157544 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-26SelectionDAGBuilder: When emitting small compare chains for switches order ↵Benjamin Kramer
them by using edge weights. SimplifyCFG tends to form a lot of 2-3 case switches when merging branches. Move the most likely condition to the front so it is checked first and the others can be skipped. This is currently not as effective as it could be because SimplifyCFG destroys profiling metadata when merging branches and switches. Merging branch weight metadata is tricky though. This code touches at most 3 cases so I didn't use a proper sorting algorithm. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157521 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-25[NVPTX] Add a new test case for the newly-enabled call handlingJustin Holewinski
NV_CONTRIB git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157485 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-25test/CodeGen/X86/bigstructret.ll: Suppress one test. It is ↵NAKAMURA Takumi
msvc-incompatible. (compatible to mingw32 and netbsd, though) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157474 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-25test/CodeGen/X86/bigstructret.ll: Relax stack offsets for hosts of ↵NAKAMURA Takumi
stack-align=8, eg. win32 and netbsd. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157471 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-25Simplify code for calling a function where CanLowerReturn fails, fixing a ↵Eli Friedman
small bug in the process. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157446 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-24Fix for CHECK-NOT misspelling.David Blaikie
Patch by Nicklas Bo Jensen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157421 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-24Remove the PTX back-end and all of its artifacts (triple, etc.)Justin Holewinski
This back-end was deprecated in favor of the NVPTX back-end. NV_CONTRIB git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157417 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-24Turn on mips16 pseudo op when compiling for mips16.Akira Hatanaka
Expand test case for this. Patch by Reed Kotler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157410 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-24Enable Mips16 compiler to compile a null program.Akira Hatanaka
First code from the Mips16 compiler. Includes trivial test program. Patch by Reed Kotler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157408 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-23Add a test case for global live range splitting.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157357 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-23Add a last resort tryInstructionSplit() to RAGreedy.Jakob Stoklund Olesen
Live ranges with a constrained register class may benefit from splitting around individual uses. It allows the remaining live range to use a larger register class where it may allocate. This is like spilling to a different register class. This is only attempted on constrained register classes. <rdar://problem/11438902> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157354 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-23Correctly deal with identity copies in RegisterCoalescer.Jakob Stoklund Olesen
Now that the coalescer keeps live intervals and machine code in sync at all times, it needs to deal with identity copies differently. When merging two virtual registers, all identity copies are removed right away. This means that other identity copies must come from somewhere else, and they are going to have a value number. Deal with such copies by merging the value numbers before erasing the copy instruction. Otherwise, we leave dangling value numbers in the live interval. This fixes PR12927. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157340 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-23[arm-fast-isel] Add support for non-global callee.Chad Rosier
Patch by Jush Lu <jush.msn@gmail.com>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157336 91177308-0d34-0410-b5e6-96231b3b80d8
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