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2012-10-01checking test case for r164811. was an omission to not check this in. this ↵Reed Kotler
was already approved git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164972 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-01Fix PR13899Michael Liao
- Update maximal stack alignment when stack arguments are prepared before a call. - Test cases are enhanced to show it's not a Win32 specific issue but a generic one. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164946 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-30Revert r164910 because it causes failures to several phase2 builds.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164911 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-30A DAGCombine optimization for merging consecutive stores. This optimization ↵Nadav Rotem
is not profitable in many cases because moden processos can store multiple values in parallel, and preparing the consecutive store requires some work. We only handle these cases: 1. Consecutive stores where the values and consecutive loads. For example: int a = p->a; int b = p->b; q->a = a; q->b = b; 2. Consecutive stores where the values are constants. Foe example: q->a = 4; q->b = 5; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164910 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-29Add LLVM support for Swift.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164899 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-29Whitespace.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164898 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-29Speculatively revert commit 164885 (nadav) in the hope of ressurecting a pile ofDuncan Sands
buildbots. Original commit message: A DAGCombine optimization for merging consecutive stores. This optimization is not profitable in many cases because moden processos can store multiple values in parallel, and preparing the consecutive store requires some work. We only handle these cases: 1. Consecutive stores where the values and consecutive loads. For example: int a = p->a; int b = p->b; q->a = a; q->b = b; 2. Consecutive stores where the values are constants. Foe example: q->a = 4; q->b = 5; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164890 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-29A DAGCombine optimization for merging consecutive stores. This optimization ↵Nadav Rotem
is not profitable in many cases because moden processos can store multiple values in parallel, and preparing the consecutive store requires some work. We only handle these cases: 1. Consecutive stores where the values and consecutive loads. For example: int a = p->a; int b = p->b; q->a = a; q->b = b; 2. Consecutive stores where the values are constants. Foe example: q->a = 4; q->b = 5; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164885 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-28Do not delete BBs if their addresses are taken. rdar://12396696Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164866 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-28MIPS DSP: add operands to make sure instruction strings are being matched.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164849 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-28MIPS DSP: other miscellaneous instructions.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164845 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-28Testcase for r164835Manman Ren
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164842 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-28MIPS DSP: ADDUH.QB instruction sub-class.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164840 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-27Enable the new coalescer algorithm by default.Jakob Stoklund Olesen
The new coalescer is better at merging values into unused vector lanes, improving NEON code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164794 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-27MIPS DSP: ABSQ_S.PH instruction sub-class.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164787 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-27MIPS DSP: SHLL.QB instruction sub-class.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164786 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-27Avoid dereferencing a NULL pointer.Jakob Stoklund Olesen
Fixes PR13943. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164778 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-27[arm-fast-isel] Add support for ELF PIC.Jush Lu
This is a preliminary step towards ELF support; currently ARMFastISel hasn't been used for ELF object files yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164759 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-27Test case for r164755 and 164756.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164757 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-27MIPS DSP: ADDU.QB instruction sub-class.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164754 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-27MIPS DSP: Branch on Greater Than or Equal To Value 32 in DSPControl Pos ↵Akira Hatanaka
Field instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164751 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-27MIPS DSP: all the remaining instructions which read or write accumulators.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164750 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-27MIPS DSP: add support for extract-word instructions.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164749 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-27MIPS DSP: add vector load/store patterns.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164744 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-26ARM/atomicrmw_minmax.ll: Fix RUN line.NAKAMURA Takumi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164687 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-26Fix ordering of operands on lowering of atomicrmw min/max nodes on ARM.James Molloy
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164685 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-26llvm/test/CodeGen/X86/mulx*.ll: Fix copypasto.NAKAMURA Takumi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164681 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-26Add SARX/SHRX/SHLX code generation supportMichael Liao
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164675 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-26Add RORX code generation supportMichael Liao
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164674 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-26Add MULX code generation supportMichael Liao
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164673 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-26Generate an error message instead of asserting or segfaulting when we have aBill Wendling
scalar-to-vector conversion that we cannot handle. For instance, when an invalid constraint is used in an inline asm statement. <rdar://problem/12284092> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164662 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-26Generate an error message instead of asserting or segfaulting when we have aBill Wendling
scalar-to-vector conversion that we cannot handle. For instance, when an invalid constraint is used in an inline asm statement. <rdar://problem/12284092> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164657 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-25Add missing i64 max/min/umax/umin on 32-bit targetMichael Liao
- Turn on atomic6432.ll and add specific test case as well git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164616 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-25Fix an illegal tailcall opt where the callee returns a double via xmm while ↵Evan Cheng
caller returns x86_fp80 via st0. rdar://12229511 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164588 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-24Mark jump tables in code sections with DataRegion directives.Jim Grosbach
Even out-of-line jump tables can be in the code section, so mark them as data-regions for those targets which support the directives. rdar://12362871&12362974 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164571 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-24Specify MachinePointerInfo as refering to the argument value and offset of theRoman Divacky
store when handling byval arguments. Thus preventing reordering of the store with load with post-RA scheduler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164553 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-23Revise test to avoid using of 'grep'Michael Liao
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164472 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-22Enhance test case of atomic16 to verify inst encoding fixed in r164453.Michael Liao
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164465 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-21[fast-isel] Fallback to SelectionDAG isel if we require strict alignment forChad Rosier
non-aligned i32 loads/stores. rdar://12304911 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164381 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-21llvm/test/CodeGen/X86/pr5145.ll: Tweak expressions to match for darwin target.NAKAMURA Takumi
.LBB0_1: # Linux LBB0_1: # Darwin git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164362 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-21Add missing i8 max/min/umax/umin supportMichael Liao
- Fix PR5145 and turn on test 8-bit atomic ops git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164358 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-21llvm/test/CodeGen/ARM/fast-isel.ll: Fix possible typos, ↵NAKAMURA Takumi
s/@unaligned_i16_store/@unaligned_i16_load/g. I guess this had apparently passed in +Asserts possibly due to verborsity. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164350 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-21Testcase does not need to be this strict.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164347 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-21Add newline.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164346 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-21[fast-isel] Fallback to SelectionDAG isel if we require strict alignment forChad Rosier
non-halfword-aligned i16 loads/stores. rdar://12304911 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164345 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-21ARM: Use a dedicated intrinsic for vector bitwise select.Jim Grosbach
The expression based expansion too often results in IR level optimizations splitting the intermediate values into separate basic blocks, preventing the formation of the VBSL instruction as the code author intended. In particular, LICM would often hoist part of the computation out of a loop. rdar://11011471 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164340 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-20Ignore PHI-defs for -new-coalescer interference checks.Jakob Stoklund Olesen
A PHI can't create interference on its own. If two live ranges interfere at a PHI, they must also interfere when leaving one of the PHI predecessors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164330 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-20Try to make these tests more portable.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164320 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-20Fix broken check lines.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164317 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-20Specify cpu to get the correct instruction ordering. Remove XFAIL.Roman Divacky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164306 91177308-0d34-0410-b5e6-96231b3b80d8
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