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AgeCommit message (Expand)Author
2011-10-28Dwarf: [PR11022] Fix emitting DW_AT_const_value(>i64), to be host-endian-neut...NAKAMURA Takumi
2011-10-28test/CodeGen/X86/2010-08-10-DbgConstant.ll: Add explicit -mtriple=i686-linux....NAKAMURA Takumi
2011-10-28Speculatively disable Dan's commits 143177 and 143179 to see ifDuncan Sands
2011-10-28Always use the string pool, even when it makes the .o larger. This may helpNick Lewycky
2011-10-28Eliminate LegalizeOps' LegalizedNodes map and have it just call RAUWDan Gohman
2011-10-27Changed test to check for correct load size instead of shift as the shift mig...Pete Cooper
2011-10-27Teach our Dwarf emission to use the string pool.Nick Lewycky
2011-10-27Don't crash on 128-bit sdiv by constant. Found by inspection.Eli Friedman
2011-10-26Run test with -verify-machineinstrs.Rafael Espindola
2011-10-26Fixes an issue reported by -verify-machineinstrs.Rafael Espindola
2011-10-26This commit introduces two fake instructions MORESTACK_RET andRafael Espindola
2011-10-23Completely re-write the algorithm behind MachineBlockPlacement based onChandler Carruth
2011-10-22Fix pr11193.Nadav Rotem
2011-10-21Fix pr11194. When promoting and splitting integers we need to useNadav Rotem
2011-10-21Don't hard code the desired alignment for loops -- it isn't 16-bytes onChandler Carruth
2011-10-211. Fix the widening of SETCC in WidenVecOp_SETCC. Use the correct return CC t...Nadav Rotem
2011-10-21Add loop aligning to MachineBlockPlacement based on review discussion soChandler Carruth
2011-10-21Add a very basic test for MachineBlockPlacement. This is essentially theChandler Carruth
2011-10-21Remove intrinsics for X86 BLSI, BLSMSK, and BLSR intrinsics and replace with ...Craig Topper
2011-10-19Fix TLS lowering bug. The CopyFromReg must be glued to the TLSCALL. rdar://10...Evan Cheng
2011-10-19Improve code generation for vselect on SSE2:Nadav Rotem
2011-10-19Add support for the vector-widening of vselect and vector-setccNadav Rotem
2011-10-19Rename PEXTR to PEXT. Add intrinsics for BMI instructions.Craig Topper
2011-10-18Added testcase for <rdar://problem/10215997>Lang Hames
2011-10-18Add additional element-promotion tests.Nadav Rotem
2011-10-18Fix a bug in the legalization of vector anyext-load and trunc-store. Mem Inde...Nadav Rotem
2011-10-17Add support for a new extension to the .file directive:Nick Lewycky
2011-10-17stabalize tests by specifying the exact sse levelNadav Rotem
2011-10-17Clean the triple, add check lines.Nadav Rotem
2011-10-17Previously v2i32 vectors were legalized to v4i32. Now, they are legalized toNadav Rotem
2011-10-16Add tripple and stabalize a few more tests.Nadav Rotem
2011-10-16Add triple to tests.Nadav Rotem
2011-10-16fix a typo in the testNadav Rotem
2011-10-16Enable element promotion type legalization by deafault.Nadav Rotem
2011-10-14Update live-in lists when splitting critical edges.Jakob Stoklund Olesen
2011-10-14Add X86 ANDN instruction. Including instruction selection.Craig Topper
2011-10-14Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 pro...Craig Topper
2011-10-14Add value numbers when spilling dead defs.Jakob Stoklund Olesen
2011-10-13Force CPU type on test so it doesn't accidentally emit movbe instead of bswap...Benjamin Kramer
2011-10-13More closely follow libgcc, which has code after the `ret' instruction toBill Wendling
2011-10-13Revert r141854 because it was causing failures:Bill Wendling
2011-10-13Should not add instructions to a BB after a return instruction. The machine i...Bill Wendling
2011-10-13Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 pro...Craig Topper
2011-10-12Also inflate register classes around inline asm.Jakob Stoklund Olesen
2011-10-12We need to verify that the machine instruction we're using as a replacement forBill Wendling
2011-10-11Make this test more specific. There are 3 stats that matched "machine-licm".Bob Wilson
2011-10-11Add a new wrapper node for a DILexicalBlock that encapsulates it and aEric Christopher
2011-10-11Add dominance check for the instruction being hoisted.Devang Patel
2011-10-11Add support for legalization of vector SHL/SRA/SRL instructionsNadav Rotem
2011-10-11Test case for X86 LZCNT instruction selection.Craig Topper
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