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2011-11-27Upgrade syntax of tests using volatile instructions to use 'load volatile' ↵Chris Lattner
instead of 'volatile load', which is archaic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145171 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-17When fast iseling a GEP, accumulate the offset rather than emitting a series ofChad Rosier
ADDs. MaxOffs is used as a threshold to limit the size of the offset. Tradeoffs being: (1) If we can't materialize the large constant then we'll cause fast-isel to bail. (2) Too large of an offset can't be directly encoded in the ADD resulting in a MOV+ADD. Generally not a bad thing because otherwise we would have had ADD+ADD, but on Thumb this turns into a MOVS+MOVT+ADD. Working on a fix for that. (3) Conversely, too low of a threshold we'll miss opportunities to coalesce ADDs. rdar://10412592 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144886 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15Add vmov.f32 to materialize f32 immediate splats which cannot be handled byEvan Cheng
integer variants. rdar://10437054 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144608 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14ARM VLDR/VSTR instructions don't need a size suffix.Jim Grosbach
Canonicallize on the non-suffixed form, but continue to accept assembly that has any correctly sized type suffix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144583 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14Add newline to end of file. Thanks, Eli.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144579 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14Add support for inlining small memcpys.Chad Rosier
rdar://10412592 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144578 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14Fix a performance regression from r144565. Positive offsets were being loweredChad Rosier
into registers, rather then encoded directly in the load/store. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144576 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14Add support for Thumb load/stores with negative offsets.Chad Rosier
rdar://10412592 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144565 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14Fix early-clobber handling in shrinkToUses.Jakob Stoklund Olesen
I broke this in r144515, it affected most ARM testers. <rdar://problem/10441389> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144547 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14Delete stale comment.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144542 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14Add support for ARM halfword load/stores and signed byte loads with negativeChad Rosier
offsets. rdar://10412592 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144518 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-13The order in which the predicate is added differs between Thumb and ARM ↵Chad Rosier
mode. Fix predicate when in ARM mode and restore SelectIntrinsicCall. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144494 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-13Temporarily disable SelectIntrinsicCall when in ARM mode. This is causing ↵Chad Rosier
failures. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144492 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-13Add support for emitting both signed- and zero-extend loads. Fix Chad Rosier
SimplifyAddress to handle either a 12-bit unsigned offset or the ARM +/-imm8 offsets (addressing mode 3). This enables a load followed by an integer extend to be folded into a single load. For example: ldrb r1, [r0] ldrb r1, [r0] uxtb r2, r1 => mov r3, r2 mov r3, r1 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144488 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-12Delete the 'standard' spiller with used the old spilling framework.Jakob Stoklund Olesen
The current register allocators all use the inline spiller. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144477 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-12RAGreedy is better about hinting now.Jakob Stoklund Olesen
Or maybe we are just getting lucky. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144473 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-12Linear scan is going away.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144472 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-12XFAIL test that depends on linear scan to remove dead code.Jakob Stoklund Olesen
Filed PR11364 to track the problem. Should the register allocator eliminate dead code? git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144471 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-12Switch a few tests off linearscan.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144460 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-12Don't try to form pre/post-indexed loads/stores until after LegalizeDAG ↵Eli Friedman
runs. Fixes PR11029. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144438 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11Add support in fast-isel for selecting memset/memcpy/memmove intrinsics.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144426 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11Loosen test by using REs. Approved by Devang.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144425 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11Preserve MachineMemOperands in ARMLoadStoreOptimizer.Andrew Trick
Fixes PR8113. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144409 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11Add support for using immediates with select instructions.Chad Rosier
rdar://10412592 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144376 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11Make sure to expand SIGN_EXTEND_INREG for NEON vectors. PR11319, round 3.Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144361 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11Add support for using MVN to materialize negative constants.Chad Rosier
rdar://10412592 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144348 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-10When in ARM mode, LDRH/STRH require special handling of negative offsets.Chad Rosier
For correctness, disable this for now. rdar://10418009 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144316 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-10For immediate encodings of icmp, zero or sign extend first. ThenChad Rosier
determine if the value is negative and flip the sign accordingly. rdar://10422026 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144258 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-09Make sure we correctly unroll conversions between v2f64 and v2i32 on ARM.Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144241 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-09Add check so we don't try to perform an impossible transformation. Fixes ↵Eli Friedman
issue from PR11319. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144216 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-09Use REs to remove dependencies on the register allocation order.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144209 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-09Add support for encoding immediates in icmp and fcmp. Hopefully, this willChad Rosier
remove a fair number of unnecessary materialized constants. rdar://10412592 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144163 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-08Add workaround for Cortex-M3 errata 602117 by replacing ldrd x, y, [x] with ↵Evan Cheng
ldm or ldr pairs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144123 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-08Lower mem-ops to unaligned i32/i16 load/stores on ARM where supported.Lang Hames
Add support for trimming constants to GetDemandedBits. This fixes some funky constant generation that occurs when stores are expanded for targets that don't support unaligned stores natively. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144102 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-08Make sure to mark vector extload's as expand on ARM. Fixes PR11319.Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144057 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-08Convert tests to the new EH model.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144048 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-08Enable support for returning i1, i8, and i16. Nothing special todo as it's theChad Rosier
callee's responsibility to sign or zero-extend the return value. The additional test case just checks to make sure the calls are selected (i.e., -fast-isel-abort doesn't assert). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144047 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-07Simplify some uses of utohexstr.Benjamin Kramer
As a side effect hex is printed lowercase instead of uppercase now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144013 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-05Add support for passing i1, i8, and i16 call parameters. Also, be sure toChad Rosier
zero-extend the constant integer encoding. Test case provides testing for both call parameters and materialization of i1, i8, and i16 types. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143821 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-05Add an option to pad an uleb128 to MCObjectWriter and remove the uleb128 ↵Benjamin Kramer
encoding from the DWARF asm printer. As a side effect we now print dwarf ulebs with .ascii directives. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143809 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-04Add fast-isel support for returning i1, i8, and i16.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143669 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-03Add support for sign-extending non-legal types in SelectSIToFP().Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143603 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-02Try to lower memset/memcpy/memmove to vector instructions on ARM where the ↵Lang Hames
alignment permits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143582 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-02Add support for comparing integer non-legal types.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143559 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-28Always use the string pool, even when it makes the .o larger. This may helpNick Lewycky
tools that read the debug info in the .o files by making the DIE sizes more consistent. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143186 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-27Also set addrmode6 alignment when align==size.Jakob Stoklund Olesen
Previously, we were only setting the alignment bits on over-aligned loads and stores. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143160 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-27Avoid partial CPSR dependency from loop backedges. rdar://10357570Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143145 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-27Teach our Dwarf emission to use the string pool.Nick Lewycky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143097 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-27A branch predicated on a constant can just FastEmit an unconditional branch.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143086 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-26Make sure short memsets on ARM lower to stores, even when optimizing for size.Lang Hames
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143055 91177308-0d34-0410-b5e6-96231b3b80d8
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