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2009-06-22Add support for ARM's Advanced SIMD (NEON) instruction set.Bob Wilson
This is still a work in progress but most of the NEON instruction set is supported. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73919 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-22It's coalescer, not coaleser.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73902 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-22For Darwin on ARMv6 and newer, make register r9 available for use as aBob Wilson
caller-saved register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73901 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-22Fix another register coalescer crash: forgot to check if the instruction ↵Evan Cheng
being updated has already been coalesced. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73898 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-22hasFP should return true if frame address is taken.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73893 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-20Fix PR4419: handle defs of partial uses.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73816 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-19Enable arm pre-allocation load / store multiple optimization pass.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73791 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-19Mark a few Thumb instructions commutable; just happened to spot this Eli Friedman
while experimenting. I'm reasonably sure this is correct, but please tell me if these instructions have some strange property which makes this change unsafe. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73746 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-17Initial support for some Thumb2 instructions.Anton Korobeynikov
Patch by Viktor Kutuzov and Anton Korzh from Access Softek, Inc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73622 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-16Make the test target-neutralAnton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73547 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-16GNU as refuses to assemble "pop {}" instruction. Do not emit suchAnton Korobeynikov
(this is the case when we have thumb vararg function with single callee-saved register, which is handled separately). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73529 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-16If a val# is defined by an implicit_def and it is being removed, all of the ↵Evan Cheng
copies off the val# were removed. This causes problem later since the scavenger will see uses of registers without defs. The proper solution is to change the copies into implicit_def's instead. TurnCopyIntoImpDef turns a copy into implicit_def and remove the val# defined by it. This causes an scavenger assertion later if the def reaches other blocks. Disable the transformation if the value live interval extends beyond its def block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73478 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-15ifcvt should ignore cfg where true and false successors are the same.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73423 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-15Part 1.Evan Cheng
- Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent. - Allow targets to specify alternative register allocation orders based on allocation hint. Part 2. - Use the register allocation hint system to implement more aggressive load / store multiple formation. - Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g. v1025 = LDR v1024, 0 v1026 = LDR v1024, 0 => v1025,v1026 = LDRD v1024, 0 If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair. - Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions. This is work in progress, not yet enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73381 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-13Add a ARM specific pre-allocation pass that re-schedule loads / stores fromEvan Cheng
consecutive addresses togther. This makes it easier for the post-allocation pass to form ldm / stm. This is step 1. We are still missing a lot of ldm / stm opportunities because of register allocation are not done in the desired order. More enhancements coming. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73291 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-12If killed register is defined by implicit_def, do not clear it since it's ↵Evan Cheng
live range may overlap another def of same register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73255 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-12Mark some pattern-less instructions as neverHasSideEffects.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73252 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-08Add testcase for register scanveger assertion fix in r72755Anton Korobeynikov
(double def due to livevars) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73096 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-05Changing allocation ordering from r3 ... r0 back to r0 ... r3. The order ↵Evan Cheng
change no longer make sense after the coalescing changes we have made since then. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72955 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-04Split the Add, Sub, and Mul instruction opcodes into separateDan Gohman
integer and floating-point opcodes, introducing FAdd, FSub, and FMul. For now, the AsmParser, BitcodeReader, and IRBuilder all preserve backwards compatability, and the Core LLVM APIs preserve backwards compatibility for IR producers. Most front-ends won't need to change immediately. This implements the first step of the plan outlined here: http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72897 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-04A value defined by an implicit_def can be liven to a use BB. This is ↵Evan Cheng
unfortunate. But register allocator still has to add it to the live-in set of the use BB. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72888 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-04Re-apply 72756 with fixes. One of those was introduced by we changed ↵Evan Cheng
MachineInstrBuilder::addReg() interface. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72826 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-03Temporarily revert 72756 for now.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72757 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-03Fold preceding / trailing base inc / dec into the single load / store as well.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72756 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-19Fix pr4058 and pr4059. Do not split i64 or double arguments between r3 andBob Wilson
the stack. Patch by Sandeep Patel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72106 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-19Fix pr4091: Add support for "m" constraint in ARM inline assembly.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72105 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-18Add nounwind to a few tests.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72002 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-12Fix pr4195: When iterating through predecessor blocks, break out of the loopBob Wilson
after finding the (unique) layout predecessor. Sometimes a block may be listed more than once, and processing it more than once in this loop can lead to inconsistent values for FtTBB/FtFBB, since the AnalyzeBranch method does not clear these values. There's no point in continuing the loop regardless. The testcase for this is reduced from the 2003-05-02-DependentPHI SingleSource test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71536 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-07Fix pr4100. Do not remove no-op copies when they are dead. The registerBob Wilson
scavenger gets confused about register liveness if it doesn't see them. I'm not thrilled with this solution, but it only comes up when there are dead copies in the code, which is something that hopefully doesn't happen much. Here is what happens in pr4100: As shown in the following excerpt from the debug output of llc, the source of a move gets reloaded from the stack, inserting a new load instruction before the move. Since that source operand is a kill, the physical register is free to be reused for the destination of the move. The move ends up being a no-op, copying R3 to R3, so it is deleted. But, it leaves behind the load to reload %reg1028 into R3, and that load is not updated to show that it's destination operand (R3) is dead. The scavenger gets confused by that load because it thinks that R3 is live. Starting RegAlloc of: %reg1025<def,dead> = MOVr %reg1028<kill>, 14, %reg0, %reg0 Regs have values: Reloading %reg1028 into R3 Last use of R3[%reg1028], removing it from live set Assigning R3 to %reg1025 Register R3 [%reg1025] is never used, removing it from live set Alternative solutions might be either marking the load as dead, or zapping the load along with the no-op copy. I couldn't see an easy way to do either of those, though. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71196 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-06Do not use register as base ptr of pre- and post- inc/dec load / store nodes.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71098 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-02Previously, RecursivelyDeleteDeadInstructions provided an optionDan Gohman
of returning a list of pointers to Values that are deleted. This was unsafe, because the pointers in the list are, by nature of what RecursivelyDeleteDeadInstructions does, always dangling. Replace this with a simple callback mechanism. This may eventually be removed if all clients can reasonably be expected to use CallbackVH. Use this to factor out the dead-phi-cycle-elimination code from LSR utility function, and generalize it to use the RecursivelyDeleteTriviallyDeadInstructions utility function. This makes LSR more aggressive about eliminating dead PHI cycles; adjust tests to either be less trivial or to simply expect fewer instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70636 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-17Rename file to have the correct suffix.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69380 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-17Use CallConvLower.h and TableGen descriptions of the calling conventionsBob Wilson
for ARM. Patch by Sandeep Patel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69371 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-16Expand GEPs in ScalarEvolution expressions. SCEV expressions can nowDan Gohman
have pointer types, though in contrast to C pointer types, SCEV addition is never implicitly scaled. This not only eliminates the need for special code like IndVars' EliminatePointerRecurrence and LSR's own GEP expansion code, it also does a better job because it lets the normal optimizations handle pointer expressions just like integer expressions. Also, since LLVM IR GEPs can't directly index into multi-dimensional VLAs, moving the GEP analysis out of client code and into the SCEV framework makes it easier for clients to handle multi-dimensional VLAs the same way as other arrays. Some existing regression tests show improved optimization. test/CodeGen/ARM/2007-03-13-InstrSched.ll in particular improved to the point where if-conversion started kicking in; I turned it off for this test to preserve the intent of the test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69258 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-14Use the output of the asm so the optimizer won'tDale Johannesen
delete it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69018 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-10move a target-specific test into its directory so it isn't run if youChris Lattner
don't configure the ARM target in. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68843 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-09Fix pr3954. The register scavenger asserts for inline assembly withBob Wilson
register destinations that are tied to source operands. The TargetInstrDescr::findTiedToSrcOperand method silently fails for inline assembly. The existing MachineInstr::isRegReDefinedByTwoAddr was very close to doing what is needed, so this revision makes a few changes to that method and also renames it to isRegTiedToUseOperand (for consistency with the very similar isRegTiedToDefOperand and because it handles both two-address instructions and inline assembly with tied registers). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68714 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-08Add testcase for PR3795.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68620 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-08Soft float support for FREM.Duncan Sands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68614 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-08Soft float support for undef. Reported by Xerxes Rånby.Duncan Sands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68607 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-06Handle 'a' modifier in ARM inline assembly.Bob Wilson
Patch by Richard Pennington. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68464 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-01Fix PR3862: Recognize some ARM-specific constraints for immediates in inlineBob Wilson
assembly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68218 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-24Do not emit comments unless -asm-verbose.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67580 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-12add no-unwind, remove duplicate run line.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66775 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-09ARM isLegalAddressImmediate should check if type is a simple type now that ↵Evan Cheng
optimizer can create values of funky scalar types. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66429 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-08Recognize triplets starting with armv5-, armv6- etc. And set the ARM arch ↵Evan Cheng
version accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66365 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-08If a MI uses the same register more than once, only mark one of them as 'kill'.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66363 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-28Last commit accidentially deleted this code.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65679 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-26The last commit was overly conservative. It's ok to reuse value that's ↵Evan Cheng
already marked livein. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65498 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-22If a use operand is marked isKill, don't forget to add kill to its live ↵Evan Cheng
interval as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65279 91177308-0d34-0410-b5e6-96231b3b80d8
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