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2010-07-08Changes to ARM tail calls, mostly cosmetic.Dale Johannesen
Add explicit testcases for tail calls within the same module. Duplicate some code to humor those who think .w doesn't apply on ARM. Leave this disabled on Thumb1, and add some comments explaining why it's hard and won't gain much. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107851 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-06Don't create neon moves in CopyRegToReg. NEONMoveFixPass will do the conversionRafael Espindola
if profitable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107673 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-02Fix incorrect asm-printing of some NEON immediates. Fix weak testcase soBob Wilson
that it checks the immediate values, not just the instructions opcodes. Radar 8110263. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107487 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-01Implement the "linker_private_weak" linkage type. This will be used forBill Wendling
Objective-C metadata types which should be marked as "weak", but which the linker will remove upon final linkage. However, this linkage isn't specific to Objective-C. For example, the "objc_msgSend_fixup_alloc" symbol is defined like this: .globl l_objc_msgSend_fixup_alloc .weak_definition l_objc_msgSend_fixup_alloc .section __DATA, __objc_msgrefs, coalesced .align 3 l_objc_msgSend_fixup_alloc: .quad _objc_msgSend_fixup .quad L_OBJC_METH_VAR_NAME_1 This is different from the "linker_private" linkage type, because it can't have the metadata defined with ".weak_definition". Currently only supported on Darwin platforms. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107433 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29Fix the handling of partial redefines in the fast register allocator.Jakob Stoklund Olesen
A partial redefine needs to be treated like a tied operand, and the register must be reloaded while processing use operands. This fixes a bug where partially redefined registers were processed as normal defs with a reload added. The reload could clobber another use operand if it was a kill that allowed register reuse. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107193 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29Fix a register scavenger crash when dealing with undefined subregs.Bob Wilson
The LowerSubregs pass needs to preserve implicit def operands attached to EXTRACT_SUBREG instructions when it replaces those instructions with copies. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107189 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29Add a VT argument to getMinimalPhysRegClass and replace the copy related usesRafael Espindola
of getPhysicalRegisterRegClass with it. If we want to make a copy (or estimate its cost), it is better to use the smallest class as more efficient operations might be possible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107140 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-28Unlike other targets, ARM now uses BUILD_VECTORs post-legalization so theyBob Wilson
can't be changed arbitrarily by the DAGCombiner without checking if it is running after legalization. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107097 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-26When splitting a VAARG, remember its alignment.Rafael Espindola
This produces terrible but correct code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106952 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25Thumb2ITBlockPass: Fix a possible dereference of an invalid iterator. This wasDaniel Dunbar
introduced in r106343, but only showed up recently (with a particular compiler & linker combination) because of the particular check, and because we have no builtin checking for dereferencing the end of an array, which is truly unfortunate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106908 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25Change if-conversion block size limit checks to add some flexibility.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106901 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24Teach EmitLiveInCopies to omit copies for unused virtual registers,Dan Gohman
and to clean up unused incoming physregs from the live-in list. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106805 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24It's possible that a flag is added to the SDNode that points back to theBill Wendling
original SDNode. This is badness. Also, this function allows one SDNode to point multiple flags to another SDNode. Badness as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106793 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24Replace a big gob of old coalescer logic with the new CoalescerPair class.Jakob Stoklund Olesen
CoalescerPair can determine if a copy can be coalesced, and which register gets merged away. The old logic in SimpleRegisterCoalescing had evolved into something a bit too convoluted. This second attempt fixes some crashes that only occurred Linux. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106769 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24Eliminate the other half of the BRCOND optimization, and updateDan Gohman
as many tests as possible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106749 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24Revert "Replace a big gob of old coalescer logic with the new CoalescerPair ↵Jakob Stoklund Olesen
class." Whiny buildbots. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106710 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24Replace a big gob of old coalescer logic with the new CoalescerPair class.Jakob Stoklund Olesen
CoalescerPair can determine if a copy can be coalesced, and which register gets merged away. The old logic in SimpleRegisterCoalescing had evolved into something a bit too convoluted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106701 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-23We are missing opportunites to use ldm. Take code like this:Bill Wendling
void t(int *cp0, int *cp1, int *dp, int fmd) { int c0, c1, d0, d1, d2, d3; c0 = (*cp0++ & 0xffff) | ((*cp1++ << 16) & 0xffff0000); c1 = (*cp0++ & 0xffff) | ((*cp1++ << 16) & 0xffff0000); /* ... */ } It code gens into something pretty bad. But with this change (analogous to the X86 back-end), it will use ldm and generate few instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106693 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-23Reinstate correct test, remove the real invalidated test.Dale Johannesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106664 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-23Remove tests invalidated by previous checkin.Dale Johannesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106663 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-22Thumb1 functions using @llvm.returnaddress were not saving the incoming LR.Bob Wilson
Radar 8031193. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106582 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21Fix PR7421: bug in kill transferring logic. It was ignoring loads / stores ↵Evan Cheng
which have already been processed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106481 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21Add missing FileCheck call.Dale Johannesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106443 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21Fix PR 7433. Silly typo in non-Darwin ARM tail callDale Johannesen
handling, plus correct R9 handling in that mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106434 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-19Disable sibcall optimization for Thumb1 for now since ↵Evan Cheng
Thumb1RegisterInfo::emitEpilogue is not expecting them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106368 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18Allow ARM if-converter to be run after post allocation scheduling.Evan Cheng
- This fixed a number of bugs in if-converter, tail merging, and post-allocation scheduler. If-converter now runs branch folding / tail merging first to maximize if-conversion opportunities. - Also changed the t2IT instruction slightly. It now defines the ITSTATE register which is read by instructions in the IT block. - Added Thumb2 specific hazard recognizer to ensure the scheduler doesn't change the instruction ordering in the IT block (since IT mask has been finalized). It also ensures no other instructions can be scheduled between instructions in the IT block. This is not yet enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106344 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18Fix an inverted condition.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106330 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18When using ADDri to get the address of a stack object, 255 is a conservativeJakob Stoklund Olesen
limit on the offset that can be materialized without using the register scavenger. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106312 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18Enable tail calls on ARM by default, with someDale Johannesen
basic tests. This has been well tested on Darwin but not elsewhere. It should work provided the linker correctly resolves B.W <label in other function> which it has not seen before, at least from llvm-based compilers. I'm leaving the arm-tail-calls switch in until I see if there's any problems because of that; it might need to be disabled for some environments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106299 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18Treat the ARM inline asm {cc} constraint as a physreg (%CPSR), just like X86Jakob Stoklund Olesen
does for {flags}. If we create virtual registers of the CCR class, RegAllocFast may try to spill them, and we can't do that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106289 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-17Remove arm_apcscc from the test files. It is the default and doing thisRafael Espindola
matches what llvm-gcc and clang now produce. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106221 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-15Remove the local register allocator.Jakob Stoklund Olesen
Please use the fast allocator instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106051 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-15Set the mtriple in some tests so that they use AAPCS.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106041 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-15Remove the arm_aapcscc marker from the tests. It is the defaultRafael Espindola
for the linux targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106029 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-15Generalize the pre-coalescing of extract_subregs feeding reg_sequences,Bob Wilson
replacing the overly conservative checks that I had introduced recently to deal with correctness issues. This makes a pretty noticable difference in our testcases where reg_sequences are used. I've updated one test to check that we no longer emit the unnecessary subreg moves. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105991 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-11Add a missing bitcast. This code used to only handle conversions betweenBob Wilson
i64 and f64 types, but now it also handle Neon vector types, so the f64 result of VMOVDRR may need to be converted to a Neon type. Radar 8084742. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105845 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-04Re-apply 105308 with fix.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105502 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-04More tail call removal.Dale Johannesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105485 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-04Remove more tail calls.Dale Johannesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105450 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-04Remove a tail call, and move some CHECKs to theDale Johannesen
functions where they belong. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105449 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-03Revert 105308.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105399 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-02Enable machine cse of instructions which define physical registers.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105308 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-28Fix some latency computation bugs: if the use is not a machine opcode do not ↵Evan Cheng
just return zero. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105061 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-27Add a -regalloc=default option that chooses a register allocator based on the -OJakob Stoklund Olesen
optimization level. This only really affects llc for now because both the llvm-gcc and clang front ends override the default register allocator. I intend to remove that code later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104904 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-27llvm can't correctly support 'H', 'Q' and 'R' modifiers. Just mark it an error.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104891 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24LR is in GPR, not tGPR even in Thumb1 mode.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104518 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-22Implement @llvm.returnaddress. rdar://8015977.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104421 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-22Recognize more BUILD_VECTORs and VECTOR_SHUFFLEs that can be implemented byBob Wilson
copying VFP subregs. This exposed a bunch of dead code in the *spill-q.ll tests, so I tweaked those tests to keep that code from being optimized away. Radar 7872877. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104415 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21Change CodeGen/ARM/2009-11-02-NegativeLane.ll to use 16-bit vector elementsBob Wilson
so that it will continue to test what it was meant to test when I commit a separate change for better support of BUILD_VECTOR and VECTOR_SHUFFLE for Neon. Fix a DAG combiner crash exposed by this test change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104380 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21Teach VirtRegRewriter to handle spilling in instructions that have multipleJakob Stoklund Olesen
definitions of the virtual register. This happens when spilling the registers produced by REG_SEQUENCE: %reg1047:5<def>, %reg1047:6<def>, %reg1047:7<def> = VLD3d8 %reg1033, 0, pred:14, pred:%reg0 The rewriter would spill the register multiple times, dead store elimination tried to keep up, but ended up cutting the branch it was sitting on. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104321 91177308-0d34-0410-b5e6-96231b3b80d8
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