| Age | Commit message (Expand) | Author |
|---|
| 2010-07-08 | Changes to ARM tail calls, mostly cosmetic. | Dale Johannesen |
| 2010-07-06 | Don't create neon moves in CopyRegToReg. NEONMoveFixPass will do the conversion | Rafael Espindola |
| 2010-07-02 | Fix incorrect asm-printing of some NEON immediates. Fix weak testcase so | Bob Wilson |
| 2010-07-01 | Implement the "linker_private_weak" linkage type. This will be used for | Bill Wendling |
| 2010-06-29 | Fix the handling of partial redefines in the fast register allocator. | Jakob Stoklund Olesen |
| 2010-06-29 | Fix a register scavenger crash when dealing with undefined subregs. | Bob Wilson |
| 2010-06-29 | Add a VT argument to getMinimalPhysRegClass and replace the copy related uses | Rafael Espindola |
| 2010-06-28 | Unlike other targets, ARM now uses BUILD_VECTORs post-legalization so they | Bob Wilson |
| 2010-06-26 | When splitting a VAARG, remember its alignment. | Rafael Espindola |
| 2010-06-25 | Thumb2ITBlockPass: Fix a possible dereference of an invalid iterator. This was | Daniel Dunbar |
| 2010-06-25 | Change if-conversion block size limit checks to add some flexibility. | Evan Cheng |
| 2010-06-24 | Teach EmitLiveInCopies to omit copies for unused virtual registers, | Dan Gohman |
| 2010-06-24 | It's possible that a flag is added to the SDNode that points back to the | Bill Wendling |
| 2010-06-24 | Replace a big gob of old coalescer logic with the new CoalescerPair class. | Jakob Stoklund Olesen |
| 2010-06-24 | Eliminate the other half of the BRCOND optimization, and update | Dan Gohman |
| 2010-06-24 | Revert "Replace a big gob of old coalescer logic with the new CoalescerPair c... | Jakob Stoklund Olesen |
| 2010-06-24 | Replace a big gob of old coalescer logic with the new CoalescerPair class. | Jakob Stoklund Olesen |
| 2010-06-23 | We are missing opportunites to use ldm. Take code like this: | Bill Wendling |
| 2010-06-23 | Reinstate correct test, remove the real invalidated test. | Dale Johannesen |
| 2010-06-23 | Remove tests invalidated by previous checkin. | Dale Johannesen |
| 2010-06-22 | Thumb1 functions using @llvm.returnaddress were not saving the incoming LR. | Bob Wilson |
| 2010-06-21 | Fix PR7421: bug in kill transferring logic. It was ignoring loads / stores wh... | Evan Cheng |
| 2010-06-21 | Add missing FileCheck call. | Dale Johannesen |
| 2010-06-21 | Fix PR 7433. Silly typo in non-Darwin ARM tail call | Dale Johannesen |
| 2010-06-19 | Disable sibcall optimization for Thumb1 for now since Thumb1RegisterInfo::emi... | Evan Cheng |
| 2010-06-18 | Allow ARM if-converter to be run after post allocation scheduling. | Evan Cheng |
| 2010-06-18 | Fix an inverted condition. | Evan Cheng |
| 2010-06-18 | When using ADDri to get the address of a stack object, 255 is a conservative | Jakob Stoklund Olesen |
| 2010-06-18 | Enable tail calls on ARM by default, with some | Dale Johannesen |
| 2010-06-18 | Treat the ARM inline asm {cc} constraint as a physreg (%CPSR), just like X86 | Jakob Stoklund Olesen |
| 2010-06-17 | Remove arm_apcscc from the test files. It is the default and doing this | Rafael Espindola |
| 2010-06-15 | Remove the local register allocator. | Jakob Stoklund Olesen |
| 2010-06-15 | Set the mtriple in some tests so that they use AAPCS. | Rafael Espindola |
| 2010-06-15 | Remove the arm_aapcscc marker from the tests. It is the default | Rafael Espindola |
| 2010-06-15 | Generalize the pre-coalescing of extract_subregs feeding reg_sequences, | Bob Wilson |
| 2010-06-11 | Add a missing bitcast. This code used to only handle conversions between | Bob Wilson |
| 2010-06-04 | Re-apply 105308 with fix. | Evan Cheng |
| 2010-06-04 | More tail call removal. | Dale Johannesen |
| 2010-06-04 | Remove more tail calls. | Dale Johannesen |
| 2010-06-04 | Remove a tail call, and move some CHECKs to the | Dale Johannesen |
| 2010-06-03 | Revert 105308. | Bob Wilson |
| 2010-06-02 | Enable machine cse of instructions which define physical registers. | Evan Cheng |
| 2010-05-28 | Fix some latency computation bugs: if the use is not a machine opcode do not ... | Evan Cheng |
| 2010-05-27 | Add a -regalloc=default option that chooses a register allocator based on the -O | Jakob Stoklund Olesen |
| 2010-05-27 | llvm can't correctly support 'H', 'Q' and 'R' modifiers. Just mark it an error. | Evan Cheng |
| 2010-05-24 | LR is in GPR, not tGPR even in Thumb1 mode. | Evan Cheng |
| 2010-05-22 | Implement @llvm.returnaddress. rdar://8015977. | Evan Cheng |
| 2010-05-22 | Recognize more BUILD_VECTORs and VECTOR_SHUFFLEs that can be implemented by | Bob Wilson |
| 2010-05-21 | Change CodeGen/ARM/2009-11-02-NegativeLane.ll to use 16-bit vector elements | Bob Wilson |
| 2010-05-21 | Teach VirtRegRewriter to handle spilling in instructions that have multiple | Jakob Stoklund Olesen |
