aboutsummaryrefslogtreecommitdiff
path: root/test/CodeGen/ARM
AgeCommit message (Collapse)Author
2011-08-03Remove underscore that's breaking linux buildbots.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136833 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-03Use MachineBranchProbabilityInfo in If-Conversion instead of its own heuristics.Jakub Staszak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136826 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-03Use byte offset, instead of element number, to access merged global.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136759 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-29Add support for the 'Q' constraint.Eric Christopher
Fixes rdar://9866494 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136523 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-29Transfer implicit operands in NEONMoveFixPass.Jakob Stoklund Olesen
Later passes /are/ using this information when running the register scavenger. This fixes the second problem in PR10520. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136440 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-29Add -verify-arm-pseudo-expand.Jakob Stoklund Olesen
This hidden llc option runs the machine code verifier after expanding ARM pseudo-instructions, but before if-conversion. The machine code verifier is much better at pointing out liveness errors that can trip up the register scavenger. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136439 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-28Handle REG_SEQUENCE with implicitly defined operands.Jakob Stoklund Olesen
Code like that would only be produced by bugpoint, but we should still handle it correctly. When a register is defined by a REG_SEQUENCE of undefs, the register itself is undef. Previously, we would create a register with uses but no defs. Fixes part of PR10520. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136401 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26FileCheck'ize test.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136135 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-18Fix a crash when building 177.mesa for armv6.Jakob Stoklund Olesen
When splitting a live range immediately before an LDR_POST instruction that redefines the address register, make sure to use the correct value number in leaveIntvBefore. We need the value number entering the instruction. <rdar://problem/9793765> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135413 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-15Remove VMOVDneon and VMOVQ, which are just aliases for VORR. This continues ↵Owen Anderson
to simplify the path towards an auto-generated disassembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135290 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14Add a testcase for r135123.Eric Christopher
Part of rdar://9761830 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135133 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13Improve codegen for select's:Evan Cheng
if (x != 0) x = 1 if (x == 1) x = 1 Previous codegen looks like this: mov r1, r0 cmp r1, #1 mov r0, #0 moveq r0, #1 The naive lowering select between two different values. It should recognize the test is equality test so it's more a conditional move rather than a select: cmp r0, #1 movne r0, #0 rdar://9758317 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135017 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-11Simplify printing of ARM shifted immediates.Jim Grosbach
Print shifted immediate values directly rather than as a payload+shifter value pair. This makes for more readable output assembly code, simplifies the instruction printer, and is consistent with how Thumb immediates are displayed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134902 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-11Add a missing test for r134882.Cameron Zwarich
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134889 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08Be more aggressive about following hints.Jakob Stoklund Olesen
RAGreedy::tryAssign will now evict interference from the preferred register even when another register is free. To support this, add the EvictionCost struct that counts how many hints are broken by an eviction. We don't want to break one hint just to satisfy another. Rename canEvict to shouldEvict, and add the first bit of eviction policy that doesn't depend on spill weights: Always make room in the preferred register as long as the evictees can be split and aren't already assigned to their preferred register. Also make the CSR avoidance more accurate. When looking for a cheaper register it is OK to use a new volatile register. Only CSR aliases that have never been used before should be avoided. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134735 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08Use ARMPseudoExpand for ARM tail calls.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134719 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07Change some ARM subtarget features to be single bit yes/no in order to sink ↵Evan Cheng
them down to MC layer. Also fix tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134590 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-02FileCheck-ize and simplify RUN lines.Chandler Carruth
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134352 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01Add support for the 'j' immediate constraint. This is conditionalized onEric Christopher
supporting the instruction that the constraint is for 'movw'. Part of rdar://9119939 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134222 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01Add support for the ARM 't' register constraint. And another testcaseEric Christopher
for the 'x' register constraint. Part of rdar://9119939 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134220 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01Add support for the 'x' constraint.Eric Christopher
Part of rdar://9307836 and rdar://9119939 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134215 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-29In the ARM global merging pass, allow extraneous alignment specifiers. This passCameron Zwarich
already makes the assumption, which is correct on ARM, that a type's alignment is less than its alloc size. This improves codegen with Clang (which inserts a lot of extraneous alignment specifiers) and fixes <rdar://problem/9695089>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134106 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-29Don't depend on the optimization reverted in r134067.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134068 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27Allow lr in the register options here.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133935 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24The Neon VCVT (between floating-point and fixed-point, Advanced SIMD) Chad Rosier
instructions can be used to match combinations of multiply/divide and VCVT (between floating-point and integer, Advanced SIMD). Basically the VCVT immediate operand that specifies the number of fraction bits corresponds to a floating-point multiply or divide by the corresponding power of 2. For example, VCVT (floating-point to fixed-point, Advanced SIMD) can replace a combination of VMUL and VCVT (floating-point to integer) as follows: Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>): vmul.f32 d16, d17, d16 vcvt.s32.f32 d16, d16 becomes: vcvt.s32.f32 d16, d16, #3 Similarly, VCVT (fixed-point to floating-point, Advanced SIMD) can replace a combinations of VCVT (integer to floating-point) and VDIV as follows: Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>): vcvt.f32.s32 d16, d16 vdiv.f32 d16, d17, d16 becomes: vcvt.f32.s32 d16, d16, #3 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133813 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-22Needs a triple.Nick Lewycky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133634 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-22Emit trailing padding on constant vectors when TargetData says that the vectorNick Lewycky
is larger than the sum of the elements (including per-element padding). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133631 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-22Test case for r133560.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133585 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-21Teach dag combine to match halfword byteswap patterns.Evan Cheng
1. (((x) & 0xFF00) >> 8) | (((x) & 0x00FF) << 8) => (bswap x) >> 16 2. ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0xff000000)>>8)|((x&0x00ff0000)<<8)) => (rotl (bswap x) 16) This allows us to eliminate most of the def : Pat patterns for ARM rev16 revsh instructions. It catches many more cases for ARM and x86. rdar://9609108 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133503 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-18rip out a ton of intrinsic modernization logic from AutoUpgrade.cpp, which isChris Lattner
for pre-2.9 bitcode files. We keep x86 unaligned loads, movnt, crc32, and the target indep prefetch change. As usual, updating the testsuite is a PITA. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133337 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-17Add an alternative rev16 pattern. We should figure out a better way to ↵Evan Cheng
handle these complex rev patterns. rdar://9609108 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133289 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-17make the asmparser reject function and type redefinitions. 'Merging' hasn't ↵Chris Lattner
been needed since llvm-gcc 3.4 days. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133248 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-17Remove support for using "foo" as symbols instead of %"foo". This is ancientChris Lattner
syntax and has been long obsolete. As usual, updating the tests is the nasty part of this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133242 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-17manually upgrade a bunch of tests to modern syntax, and remove some thatChris Lattner
are either unreduced or only test old syntax. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133228 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-17Update an insertion point iterator after replacing a return instruction with aCameron Zwarich
tail call pseudoinstruction. This fixes <rdar://problem/9624333>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133227 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-16Force a triple here so this test doesn't fail on EABI hosts (like ↵Eli Friedman
clang-native-arm-cortex-a9). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133134 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-16Typos.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133128 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-16Revision r128665 added an optimization to make use of NEON multiplierChad Rosier
accumulator forwarding. Specifically (from SVN log entry): Distribute (A + B) * C to (A * C) + (B * C) to make use of NEON multiplier accumulator forwarding: vadd d3, d0, d1 vmul d3, d3, d2 => vmul d3, d0, d2 vmla d3, d1, d2 Make sure it catches cases where operand 1 is add/fadd/sub/fsub, which was intended in the original revision. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133127 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-15Testcase for previous commit.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133089 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-15Another revsh pattern. rdar://9609059Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133064 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-15PerformBFICombine - (bfi A, (and B, Mask1), Mask2) -> (bfi A, B, Mask2) iffEvan Cheng
the bits being cleared by the AND are not demanded by the BFI. The previous BFI dag combine rule was actually incorrect (or used to be correct until BFI representation changed). rdar://9609030 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133034 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-14Add an optimization that looks for a specific pair-wise add pattern and ↵Tanya Lattner
generates a vpaddl instruction instead of scalarizing the add. Includes a test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133027 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-14Since ARM's prefetch implementation predicted the presence of a instructionBruno Cardoso Lopes
cache prefetch and now that the info from "prefetch" to "ARMPreload" is present, only add a testcase for PLI. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132978 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-14Add one more argument to the prefetch intrinsic to indicate whether it's a dataBruno Cardoso Lopes
or instruction cache access. Update the targets to match it and also teach autoupgrade. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132976 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-13Be less aggressive about hinting in RAFast.Jakob Stoklund Olesen
In particular, don't spill dirty registers only to satisfy a hint. It is not worth it. The attached test case provides an example where the fast allocator would spill a register when other registers are available. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132900 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-09A CCState was being created without setting whether it is in the Call or ↵Cameron Zwarich
Prologue state, causing an assertion failure downstream. This fixes <rdar://problem/9562908>. This really seems like it should always be set at CCState creation time, so mistakes like this can never happen. I'll take a look at doing that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132811 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-03Another possible bug. Stopgap until we can autogenerate tables andEric Christopher
constraint lengths. Part of rdar://9037836 and rdar://9119939 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132598 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-03Fix an off by one error.Eric Christopher
Part of rdar://9037836 and rdar://9119939 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132590 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-03Make the Uv constraint a memory operand. This doesn't solve theEric Christopher
addressing mode problem mentioned in r132559. Backend part of rdar://9037836 and part of rdar://9119939 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132561 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-03Add ARM fast-isel support for materializing the address of a global in cases ↵Eli Friedman
where the global uses an indirect symbol. rdar://9431157 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132522 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.2.3-70-g09d2 (git 2.46.0) at 2026-01-05 06:35:56 +0000