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AgeCommit message (Expand)Author
2013-03-27R600/SI: add mulhu/mulhs patternsChristian Konig
2013-03-27R600/SI: add srl/sha patterns for SIChristian Konig
2013-03-27Allocate r0 on PPCHal Finkel
2013-03-27Use the PPC no-r0 class on the TOC LD pseudosHal Finkel
2013-03-27Apply the no-r0 register class to the PPC SELECT_CC_I[4|8] pseudosHal Finkel
2013-03-27Apply the no-r0 class to PPC TOC ADDI[S] pseudo instructionsHal Finkel
2013-03-27Remove the link register from the GPR classes on PowerPC.Bill Schmidt
2013-03-27Adding DIImportedModules to DIScopes.David Blaikie
2013-03-27Don't spill PPC VRSAVE on non-Darwin (even in SjLj)Hal Finkel
2013-03-26Make DIBuilder::createClassType more type safe by returning DICompositeType r...David Blaikie
2013-03-26DebugInfo: more support for mutating DICompositeType to reduce magic number u...David Blaikie
2013-03-26Add a boolean parameter to the ExecuteAndWait static function to indicatedChad Rosier
2013-03-26Use the full path when outputting the `.gcda' file.Bill Wendling
2013-03-26Add XTEST codegen supportMichael Liao
2013-03-26Add HLE target featureMichael Liao
2013-03-26Enable SandyBridgeModel for all modern Intel P6 descendants.Jakob Stoklund Olesen
2013-03-26Debug Info: Provide a means to update the members of a composite typeDavid Blaikie
2013-03-26Restore real bit lengths on PPC register numbersHal Finkel
2013-03-26Fix the register scavenger for targets that provide custom spillingHal Finkel
2013-03-26PNaCl: Add ExpandGetElementPtr pass for converting GetElementPtr to arithmeticMark Seaborn
2013-03-26PPC: Use HWEncoding and TRI->getEncodingValueHal Finkel
2013-03-26R600/SIMCCodeEmitter.cpp: Prune a couple of unused members, STI and Ctx. [-Wu...NAKAMURA Takumi
2013-03-26Use multiple virtual registers in PPC CR spillingHal Finkel
2013-03-26Update PPCRegisterInfo's use of virtual registers to be SSAHal Finkel
2013-03-26Update PEI's virtual-register-based scavenging to support multiple simultaneo...Hal Finkel
2013-03-26Annotate the remaining x86 instructions with SchedRW lists.Jakob Stoklund Olesen
2013-03-26Annotate x87 and mmx instructions with SchedRW lists.Jakob Stoklund Olesen
2013-03-26Annotate control instructions with SchedRW lists.Jakob Stoklund Olesen
2013-03-26Annotate the rest of X86InstrInfo.td with SchedRW lists.Jakob Stoklund Olesen
2013-03-26BasicAA: Only query twice if the result of the more general query was MayAliasArnold Schwaighofer
2013-03-26Add PREFETCHW codegen supportMichael Liao
2013-03-26Hexagon: Use multiclass for aslh, asrh, sxtb, sxth, zxtb and zxth.Jyotsna Verma
2013-03-26Make InstCombineCasts.cpp:OptimizeIntToFloatBitCast endian safe.Ulrich Weigand
2013-03-26Hexagon: Remove HexagonMCInst.h file. It has been replaced with MCTargetDesc/...Jyotsna Verma
2013-03-26Revert ARM Scheduler Model: Add resources instructions, map resourcesArnold Schwaighofer
2013-03-26Remove default case from fully covered switch.Benjamin Kramer
2013-03-26R600/SI: improve post ISel foldingChristian Konig
2013-03-26R600/SI: improve vector interpolationChristian Konig
2013-03-26R600/SI: avoid unecessary subreg extraction in IMAGE_SAMPLEChristian Konig
2013-03-26R600/SI: switch back to RegPressure schedulingChristian Konig
2013-03-26R600/SI: mark most intrinsics as readnone v2Christian Konig
2013-03-26R600/SI: replace WQM intrinsicChristian Konig
2013-03-26R600/SI: fix ELSE pseudo op handlingChristian Konig
2013-03-26Patch by Gordon Keiser!Joe Abbey
2013-03-26[ASan] Change the ABI of __asan_before_dynamic_init function: now it takes po...Alexey Samsonov
2013-03-26PowerPC: Mark patterns as isCodeGenOnly.Ulrich Weigand
2013-03-26PowerPC: Simplify handling of fixups.Ulrich Weigand
2013-03-26PowerPC: Simplify FADD in round-to-zero mode.Ulrich Weigand
2013-03-26PowerPC: Remove LDrs pattern.Ulrich Weigand
2013-03-26PowerPC: Remove ADDIL patterns.Ulrich Weigand
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