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2012-05-07Add support for the 'l' constraint.Eric Christopher
Patch by Jack Carter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156294 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-07Add support for the 'c' constraint.Eric Christopher
Patch by Jack Carter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156293 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-07Add support for the 'P' constraint.Eric Christopher
Patch by Jack Carter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156292 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-07Fix some issues in the f16c instructions.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156287 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-07Add support for the 'O' constraint.Eric Christopher
Patch by Jack Carter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156285 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-07Add support for the 'N' inline asm constraint.Eric Christopher
Patch by Jack Carter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156284 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-07Add support for the 'L' inline asm constraint.Eric Christopher
Patch by Jack Carter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156283 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-07Add support for the inline asm constraint 'K'.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156282 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-07Add SSE4A MOVNTSS/MOVNTSD instructions.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156281 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-07Support the 'J' constraint.Eric Christopher
Patch by Jack Carter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156280 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-07Add support for the 'I' inline asm constraint. Also add testsEric Christopher
from the previous 2 patches. Patch by Jack Carter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156279 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-07Allow 64 bit integer values in gpu registers if arch and abi are 64 bit.Eric Christopher
Patch by Jack Carter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156278 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-07When using inline asm constraints representingEric Christopher
non-floating point general registers allow 8 and 16-bit elements. Patch by Jack Carter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156277 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-06Use MVT instead of EVT as the argument to all the shuffle decode functions. ↵Craig Topper
Simplify some of the decode functions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156268 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-06Add VPERMQ/VPERMPD to the list of target specific shuffles that can be ↵Craig Topper
looked through for DAG combine purposes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156266 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-06Add shuffle decode support for VPERMQ/VPERMPD.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156265 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-05Nuke a few dead remnants of the CBE.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156241 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-05Add a new target hook "predictableSelectIsExpensive".Benjamin Kramer
This will be used to determine whether it's profitable to turn a select into a branch when the branch is likely to be predicted. Currently enabled for everything but Atom on X86 and Cortex-A9 devices on ARM. I'm not entirely happy with the name of this flag, suggestions welcome ;) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156233 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-05NVPTX: Initialize the UseF32FTZ flag.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156232 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-05Typo.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156226 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-04Fix warnings in release build.David Blaikie
This fixes a couple of Clang warnings in release builds of LLVM: * Missing return in ISelLowering * Unused variable in NVPTXutil.cpp git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156216 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-04Tweak to the fix in r156212, as with the change in removing the shift theKevin Enderby
SignExtend32<22>(Val<<1) also needs to change to SignExtend32<21>(Val) . git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156213 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-04Fix a bug in the ARM disassembler for wide branch conditional instructionsKevin Enderby
where the symbolic operand's displacement was incorrectly shifted left by 1. rdar://11387046 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156212 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-04Fix a Clang warning in the new NVPTX backend:Chandler Carruth
In file included from ../lib/Target/NVPTX/VectorElementize.cpp:53: ../lib/Target/NVPTX/NVPTX.h:44:3: warning: default label in switch which covers all enumeration values [-Wcovered-switch-default] default: assert(0 && "Unknown condition code"); ^ 1 warning generated. The prevailing pattern in LLVM is to not use a default label, and instead to use llvm_unreachable to denote that the switch in fact covers all return paths from the function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156209 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-04This patch adds a new NVPTX back-end to LLVM which supports code generation ↵Justin Holewinski
for NVIDIA PTX 3.0. This back-end will (eventually) replace the current PTX back-end, while maintaining compatibility with it. The new target machines are: nvptx (old ptx32) => 32-bit PTX nvptx64 (old ptx64) => 64-bit PTX The sources are based on the internal NVIDIA NVPTX back-end, and contain more functionality than the current PTX back-end currently provides. NV_CONTRIB git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156196 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-04Added missing CMN case in Thumb2SizeReduction pass so that LLVM emits ↵Sebastian Pop
16-bits encoding of CMN instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156195 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-04Adds Intel Atom scheduling latencies to X86InstrSystem.td.Preston Gurd
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156194 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-04Pacify GCC's -Wreturn-typeMatt Beaumont-Gay
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156189 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-04Make ARM and Mips use TargetMachine::getTLSModel()Hans Wennborg
This moves the logic for selecting a TLS model to a single place, instead of the previous three (ARM, Mips, and X86 which already uses this function). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156162 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-04Fix some loops to match coding standards. No functional change intended.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156159 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-04Fix up some spacing. No functional change.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156158 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-04Simplify broadcast lowering code. No functional change intended.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156157 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-04Allow v16i16 and v32i8 shuffles to be rewritten as narrower shuffles.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156156 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-04Simplify shuffle narrowing code a bit. No functional change intended.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156154 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-04Remove the SubRegClasses field from RegisterClass descriptions.Jakob Stoklund Olesen
This information in now computed by TableGen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156152 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-04Initialize SparcInstrInfo before SparcTargetLowering.Jakob Stoklund Olesen
The TargetLowering construction needs to use a valid TargetRegisterInfo instance. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156146 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-04Add a SuperRegClassIterator class.Jakob Stoklund Olesen
This iterator class provides a more abstract interface to the (Idx, Mask) lists of super-registers for a register class. The layout of the tables shouldn't be exposed to clients. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156144 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-03Use a shared implementation of getMatchingSuperRegClass().Jakob Stoklund Olesen
TargetRegisterClass now gives access to the necessary tables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156122 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-03Fix issues with the ARM bl and blx thumb instructions and the J1 and J2 bitsKevin Enderby
for the assembler and disassembler. Which were not being set/read correctly for offsets greater than 22 bits in some cases. Changes to lib/Target/ARM/ARMAsmBackend.cpp from Gideon Myles! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156118 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-03Support for target dependent Hexagon VLIW packetizer.Sirish Pande
This patch creates and optimizes packets as per Hexagon ISA rules. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156109 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-03Fixed disassembler for vstm/vldm ARM VFP instructions.Silviu Baranga
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156077 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-03Extensions of Hexagon V4 instructions.Sirish Pande
This adds new instructions for Hexagon V4 architecture. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156071 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-03Use 'unsigned' instead of 'int' in a few places dealing with counts of ↵Craig Topper
vector elements. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156060 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-03Fix 256-bit vpshuflw and vpshufhw immediate encoding to handle undefs in the ↵Craig Topper
lower half correctly. Missed in r155982. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156059 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-03Added TargetRegisterInfo::getAllocatableClass.Andrew Trick
The ensures that virtual registers always belong to an allocatable class. If your target attempts to create a vreg for an operand that has no allocatable register subclass, you will crash quickly. This ensures that targets define register classes as intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156046 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-02For Intel Atom, use ILP scheduling always, instead of ILP for 64 bitPreston Gurd
and Hybrid for 32 bit, since benchmarks show ILP scheduling is better most of the time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156028 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-02Change the Intel Atom detection code to recognizePreston Gurd
Lincroft and Medfield. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156025 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-02ARM: Add missing two-operand VBIC aliases.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156019 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-02This patch continues the work of adding instruction latencies for X86 Atom,Preston Gurd
by providing the latencies for the instructions in X86InstrFPStack.td. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155996 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-02Revert r155853Manman Ren
The commit is intended to fix rdar://10961709. But it is the root cause of PR12720. Revert it for now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155992 91177308-0d34-0410-b5e6-96231b3b80d8
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