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AgeCommit message (Expand)Author
2012-07-18whitespaceAndrew Trick
2012-07-18The vbroadcast family of instructions has 'fallback patterns' in case where theNadav Rotem
2012-07-18Mips specific inline asm operand modifier 'M':Jack Carter
2012-07-18Remove tab characters.Craig Topper
2012-07-18Fix typo in error message and remove some tab characters.Craig Topper
2012-07-18Make x86 asm parser to check for xmm vs ymm for index register in gather inst...Craig Topper
2012-07-18More replacing of target-dependent intrinsics with target-indepdent Joel Jones
2012-07-17Clean up Mips16InstrFormats.td and Mips16InstrInfo.td.Akira Hatanaka
2012-07-17Back out r160101 and instead implement a dag combine to recover from instcomb...Evan Cheng
2012-07-17Implement r160312 as target indepedenet dag combine.Evan Cheng
2012-07-17This is another case where instcombine demanded bits optimization createdEvan Cheng
2012-07-16For something likeEvan Cheng
2012-07-16Revert "AMDGPU: Add core backend files for R600/SI codegen v6"Tom Stellard
2012-07-16Revert "Build script changes for R600/SI Codegen v6"Tom Stellard
2012-07-16Revert "Target/AMDGPU/R600KernelParameters.cpp: Fix two includes, <llvm/IRBui...Tom Stellard
2012-07-16Revert "Target/AMDGPU: [CMake] Fix dependencies. 1) Add intrinsics_gen. Add A...Tom Stellard
2012-07-16Revert "Target/AMDGPU/R600KernelParameters.cpp: Don't use "and", "or" as cond...Tom Stellard
2012-07-16Revert "Target/AMDGPU/AMDILIntrinsicInfo.cpp: Use llvm_unreachable() in nonre...Tom Stellard
2012-07-16Revert "Target/AMDGPU: Fix includes, or msvc build failed."Tom Stellard
2012-07-16With r160248 in place this code is no longer needed.Chad Rosier
2012-07-16Target/AMDGPU: Fix includes, or msvc build failed.NAKAMURA Takumi
2012-07-16Target/AMDGPU/AMDILIntrinsicInfo.cpp: Use llvm_unreachable() in nonreturn fun...NAKAMURA Takumi
2012-07-16Target/AMDGPU/R600KernelParameters.cpp: Don't use "and", "or" as conditional ...NAKAMURA Takumi
2012-07-16Doubleword Shift Left Logical Plus 32Jack Carter
2012-07-16Target/AMDGPU: [CMake] Fix dependencies. 1) Add intrinsics_gen. Add AMDGPUCom...NAKAMURA Takumi
2012-07-16Target/AMDGPU/R600KernelParameters.cpp: Fix two includes, <llvm/IRBuilder.h> ...NAKAMURA Takumi
2012-07-16Build script changes for R600/SI Codegen v6Tom Stellard
2012-07-16AMDGPU: Add core backend files for R600/SI codegen v6Tom Stellard
2012-07-16Fix a bug in the 3-address conversion of LEA when one of the operands is anNadav Rotem
2012-07-16This CL changes the function prologue and epilogue emitted on X86 when stack ...Alexey Samsonov
2012-07-15Teach getTargetVShiftNode about TargetConstant nodes.Nadav Rotem
2012-07-15Rename VBROADCASTSDrm into VBROADCASTSDYrm to match the naming convention.Nadav Rotem
2012-07-14AVX: Fix a bug in getTargetVShiftNode. The shift amount has to be a 128bit ve...Nadav Rotem
2012-07-13This is one of the first steps at moving to replace target-dependent Joel Jones
2012-07-13Remove variable_ops from call instructions in most targets.Jakob Stoklund Olesen
2012-07-13Remove variable_ops from ARM call instructions.Jakob Stoklund Olesen
2012-07-13The Mips specific relocation R_MIPS_GOT_DISP Jack Carter
2012-07-13Make helper functions static.Benjamin Kramer
2012-07-13Mark VINSERTI128rm as MayLoad=1. Fixes PR13348.Craig Topper
2012-07-12Give the rdrand instructions a SideEffect flag and a chain so MachineCSE and ...Benjamin Kramer
2012-07-12Add intrinsics for Ivy Bridge's rdrand instruction.Benjamin Kramer
2012-07-12Update GATHER instructions to support 2 read-write operands. Patch from mysel...Craig Topper
2012-07-11ARM: fix typo in commentsManman Ren
2012-07-11ARM: Fix optimizeCompare to correctly check safe condition.Manman Ren
2012-07-11Patch for Mips direct object generation.Jack Carter
2012-07-11This change removes an "initialization" warning.Jack Carter
2012-07-11In register classes in MipsRegisterInfo.td, list the registers in ascendingAkira Hatanaka
2012-07-11[x86 fast-isel] Per discussion with Eric, add all cases to switch with verboseChad Rosier
2012-07-11X86: Update to peephole optimization to move Movr0 before (Sub, Cmp) pair.Manman Ren
2012-07-11Implement MipsTargetLowering::LowerSELECT_CC to custom lower SELECT_CC.Akira Hatanaka
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