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2012-12-04Move all operand definitions into HexagonOperands.tdJyotsna Verma
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169213 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-04Move generic Hexagon subtarget information into Hexagon.tdJyotsna Verma
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169212 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-04Remove the old TRI::ResolveRegAllocHint() and getRawAllocationOrder() hooks.Jakob Stoklund Olesen
These functions have been replaced by TRI::getRegAllocationHints() which provides the same capabilities. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169192 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-03Classic JIT is still being supported by MIPS, along with MCJIT.Akira Hatanaka
This change adds endian-awareness to MipsJITInfo and emitWordLE in MipsCodeEmitter has become emitWord now to support both endianness. Patch by Petar Jovanovic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169177 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-03Functions in MipsCodeEmitter.cpp that expand unaligned loads/stores are deadAkira Hatanaka
code. Removing it. Patch by Petar Jovanovic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169174 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-03Implement ARMBaseRegisterInfo::getRegAllocationHints().Jakob Stoklund Olesen
This provides the same functionality as getRawAllocationOrder() for the even/odd hints, but without the many constant register arrays. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169169 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-03Define store instructions with base+immediate offset addressing modeJyotsna Verma
using multiclass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169168 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-03Define load instructions with base+immediate offset addressing modeJyotsna Verma
using multiclass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169153 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-03Define unsigned const-ext predicates.Jyotsna Verma
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169149 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-03Removing unnecessary 'else' statement from the predicates defined in ↵Jyotsna Verma
HexagonOperards.td. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169148 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-03Use the new script to sort the includes of every file under lib.Chandler Carruth
Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-03Define signed const-ext predicates.Jyotsna Verma
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169117 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-30Codegen failure for vmull with small vectorsSebastian Pop
Codegen was failing with an assertion because of unexpected vector operands when legalizing the selection DAG for a MUL instruction. The asserting code was legalizing multiplies for vectors of size 128 bits. It uses a custom lowering to try and detect cases where it can use a VMULL instruction instead of a VMOVL + VMUL. The code was looking for input operands to the MUL that had been sign or zero extended. If it found the extended operands it would drop the sign/zero extension and use the original vector size as input to a VMULL instruction. The code assumed that the original input vector was 64 bits so that after dropping the extension it would fit directly into a D register and could be used as an operand of a VMULL instruction. The input code that trigger the failure used a vector of <4 x i8> that was sign extended to <4 x i32>. It was not safe to drop the sign extension in this case because the original vector is only 32 bits wide. The fix is to insert a sign extension for the vector to reach the required 64 bit size. In this particular example, the vector would need to be sign extented to a <4 x i16>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169024 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-30Use isOSNaCl and minimize some LOCALMODsDavid Sehr
Another try after fumble-fingering git repos for https://codereview.chromium.org/11428097/ BUG= Review URL: https://codereview.chromium.org/11415231
2012-11-30Use multiclass for the load instructions with MEMri operand.Jyotsna Verma
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169018 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-30This patch fixes the Altivec addend construction for the fused multiply-addAdhemerval Zanella
instruction (vmaddfp) to conform with IEEE to ensure the sign of a zero result when resulting product is -0.0. The -0.0 vector addend to vmaddfp is generated by a creating a vector with full bits sets and then shifting each elements by 31-bits to the left, resulting in a vector of 0x80000000 (or -0.0 as float). The 'buildvec_canonicalize.ll' was adjusted to reflect this change and the 'vec_mul.ll' was complemented with the float vector multiplication test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168998 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-30Switch LLVM_USE_RVALUE_REFERENCES to LLVM_HAS_RVALUE_REFERENCES.Chandler Carruth
Rationale: 1) This was the name in the comment block. ;] 2) It matches Clang's __has_feature naming convention. 3) It matches other compiler-feature-test conventions. Sorry for the noise. =] I've also switch the comment block to use a \brief tag and not duplicate the name. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168996 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-30Use multiclass for the store instructions with MEMri operand.Jyotsna Verma
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168983 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-30Use multiclass for the load instructions with 'base + register offset'Jyotsna Verma
addressing mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168976 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-29Fixed the arm disassembly of invalid BFI instructions to not build a bad MCInstKevin Enderby
which would then cause an assert when printed. rdar://11437956 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168960 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-29Cleanup for comprehensibility:Eli Bendersky
- Removed outdated/wrong information - Added more comments to explain what's going on - Cleaned up the control flow with assertions instead of conditions for impossible paths BUG=none Review URL: https://codereview.chromium.org/11280222
2012-11-29Add isOSNaCl, and add Asm subclasses for NaClDavid Sehr
Removes some of the FIXME cruft that suggest we should use subclassing. BUG= Review URL: https://codereview.chromium.org/11316230
2012-11-29Leave NOPS as upstream definesDavid Sehr
Upstream tests fail because NOPS are expected to be 0xe1a00000 rather than what we substitute. This seems to have been a performance only fix, and the ARM manuals are quite ambiguous about which to prefer for performance anyway. I am reverting to the upstream version. BUG= http://code.google.com/p/nativeclient/issues/detail?id=1711 Review URL: https://codereview.chromium.org/11280193
2012-11-29Conditionalize delay slot hazard checksDavid Sehr
Filling the delay slot should not check for NaCl hazards unless the triple is for NaCl. BUG= http://code.google.com/p/nativeclient/issues/detail?id=1711 Review URL: https://codereview.chromium.org/11299215
2012-11-29Add cortex-a5 subtarget to the supported ARM architecturesQuentin Colombet
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168933 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-29rdar://12100355 (part 1)Shuxin Yang
This revision attempts to recognize following population-count pattern: while(a) { c++; ... ; a &= a - 1; ... }, where <c> and <a>could be used multiple times in the loop body. TODO: On X8664 and ARM, __buildin_ctpop() are not expanded to a efficent instruction sequence, which need to be improved in the following commits. Reviewed by Nadav, really appreciate! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168931 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-29Use multiclass for 'transfer' instructions.Jyotsna Verma
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168929 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-29Conditionalize MIPS register reservationDavid Sehr
The MIPS code generator reserves three extra registers for sandbox use. Make sure these are only reserved if NaCl is being targeted. BUG= http://code.google.com/p/nativeclient/issues/detail?id=1711 Review URL: https://codereview.chromium.org/11308232
2012-11-29Disable register-register preloads for NaCl.JF Bastien
This disables, prefetches using the base reg + index reg ("[rb, ri]") style addressing mode. We do not allow this addressing mode for other memory instructions either and just to make sure we would also like to sandbox this instruction which is only possible for the base + immediate offset addressing mode. R=dschuff@chromium.org BUG=https://code.google.com/p/nativeclient/issues/detail?id=3117 TEST=nacl_compiler_test/gcc-4.6.1/gcc/testsuite/gcc.c-torture/execute/builtin-prefetch-1.c TEST=nacl_compiler_test/gcc-4.6.1/gcc/testsuite/gcc.c-torture/execute/builtin-prefetch-3.c TEST=nacl_compiler_test/gcc-4.6.1/gcc/testsuite/gcc.c-torture/execute/builtin-prefetch-4.c TEST=nacl_compiler_test/gcc-4.6.1/gcc/testsuite/gcc.c-torture/execute/builtin-prefetch-5.c TEST=nacl_compiler_test/gcc-4.6.1/gcc/testsuite/gcc.c-torture/execute/builtin-prefetch-6.c TEST=test/CodeGen/ARM/prefetch.ll Review URL: https://codereview.chromium.org/11416141
2012-11-29Fix LibCall simplification and ARM EHDerek Schuff
Prevent the libcall simplifier from modifying the implementation of libcalls (causes problems when newlib is included in LTO) Use the generic DWARF rather than ARM EH ABI for nacl
2012-11-29Merge remote-tracking branch 'origin/master' into merge168633Derek Schuff
2012-11-29Removing unused code for computing CPSR liveness for sandboxing.Eli Bendersky
BUG= http://code.google.com/p/nativeclient/issues/detail?id=3160 Review URL: https://codereview.chromium.org/11421129
2012-11-29Added atomic 64 min/max/umin/umax instrinsics support in the ARM backend.Silviu Baranga
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168886 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-29Allow targets to prefer TypeSplitVector over TypePromoteInteger when ↵Justin Holewinski
computing the legalization method for vectors For some targets, it is desirable to prefer scalarizing <N x i1> instead of promoting to a larger legal type, such as <N x i32>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168882 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-29I changed hasAVX() to hasFp256() and hasAVX2() to hasInt256() in ↵Elena Demikhovsky
X86IselLowering.cpp. The logic was not changed, only names. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168875 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-28Define signed const-ext immediate operands and their predicates.Jyotsna Verma
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168810 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-28ARM: Implement CanLowerReturn so large vectors get expanded into sret.Benjamin Kramer
Fixes 14337. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168809 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-28Fix initial frame state on powerpc64.Ulrich Weigand
The createPPCMCAsmInfo routine used PPC::R1 as the initial frame pointer register, but on PPC64 the 32-bit R1 register does not have a corresponding DWARF number, causing invalid CIE initial frame state to be emitted. Fix by using PPC::X1 instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168799 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-28Remove all references to TargetInstrInfoImpl.Jakob Stoklund Olesen
This class has been merged into its super-class TargetInstrInfo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168760 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-28Move Target{Instr,Register}Info.cpp into lib/CodeGen.Jakob Stoklund Olesen
The Target library is not allowed to depend on the large CodeGen library, but the TRI and TII classes provide abstract interfaces that require both caller and callee to link to CodeGen. The implementation files for these classes provide default implementations of some of the hooks. These methods may need to reference CodeGen, so they belong in that library. We already have a number of methods implemented in the TargetInstrInfoImpl sub-class because of that. I will merge that class into the parent next. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168758 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-27This patch makes medium code model the default for 64-bit PowerPC ELF.Bill Schmidt
When the CodeGenInfo is to be created for the PPC64 target machine, a default code-model selection is converted to CodeModel::Medium provided we are not targeting the Darwin OS. Defaults for Darwin are unaffected. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168747 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-27[arm fast-isel] Appease the machine verifier by using the proper registerChad Rosier
classes. The vast majority of the remaining issues are due to uses of invalid registers, which are defined by getRegForValue(). Those will be a little more challenging to cleanup. rdar://12719844 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168735 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-27[arm fast-isel] Appease the machine verifier by using the proper registerChad Rosier
classes. rdar://12719844 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168733 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-27[arm fast-isel] Appease the machine verifier by using the proper registerChad Rosier
classes. Also a bit of cleanup. rdar://12719844 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168728 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-27Merge commit '8d20b5f9ff609e70fae5c865931ab0f29e639d9c'Derek Schuff
Conflicts: lib/CodeGen/AsmPrinter/DwarfDebug.cpp lib/CodeGen/AsmPrinter/DwarfDebug.h lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp lib/Target/Mips/MipsISelDAGToDAG.cpp lib/Target/Mips/MipsInstrFPU.td lib/Target/Mips/MipsSubtarget.cpp lib/Target/Mips/MipsSubtarget.h lib/Target/X86/X86MCInstLower.cpp tools/Makefile tools/llc/llc.cpp
2012-11-27X86: do not fold load instructions such as [V]MOVS[S|D] to other instructionsManman Ren
when the destination register is wider than the memory load. These load instructions load from m32 or m64 and set the upper bits to zero, while the folded instructions may accept m128. rdar://12721174 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168710 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-27This patch implements medium code model support for 64-bit PowerPC.Bill Schmidt
The default for 64-bit PowerPC is small code model, in which TOC entries must be addressable using a 16-bit offset from the TOC pointer. Additionally, only TOC entries are addressed via the TOC pointer. With medium code model, TOC entries and data sections can all be addressed via the TOC pointer using a 32-bit offset. Cooperation with the linker allows 16-bit offsets to be used when these are sufficient, reducing the number of extra instructions that need to be executed. Medium code model also does not generate explicit TOC entries in ".section toc" for variables that are wholly internal to the compilation unit. Consider a load of an external 4-byte integer. With small code model, the compiler generates: ld 3, .LC1@toc(2) lwz 4, 0(3) .section .toc,"aw",@progbits .LC1: .tc ei[TC],ei With medium model, it instead generates: addis 3, 2, .LC1@toc@ha ld 3, .LC1@toc@l(3) lwz 4, 0(3) .section .toc,"aw",@progbits .LC1: .tc ei[TC],ei Here .LC1@toc@ha is a relocation requesting the upper 16 bits of the 32-bit offset of ei's TOC entry from the TOC base pointer. Similarly, .LC1@toc@l is a relocation requesting the lower 16 bits. Note that if the linker determines that ei's TOC entry is within a 16-bit offset of the TOC base pointer, it will replace the "addis" with a "nop", and replace the "ld" with the identical "ld" instruction from the small code model example. Consider next a load of a function-scope static integer. For small code model, the compiler generates: ld 3, .LC1@toc(2) lwz 4, 0(3) .section .toc,"aw",@progbits .LC1: .tc test_fn_static.si[TC],test_fn_static.si .type test_fn_static.si,@object .local test_fn_static.si .comm test_fn_static.si,4,4 For medium code model, the compiler generates: addis 3, 2, test_fn_static.si@toc@ha addi 3, 3, test_fn_static.si@toc@l lwz 4, 0(3) .type test_fn_static.si,@object .local test_fn_static.si .comm test_fn_static.si,4,4 Again, the linker may replace the "addis" with a "nop", calculating only a 16-bit offset when this is sufficient. Note that it would be more efficient for the compiler to generate: addis 3, 2, test_fn_static.si@toc@ha lwz 4, test_fn_static.si@toc@l(3) The current patch does not perform this optimization yet. This will be addressed as a peephole optimization in a later patch. For the moment, the default code model for 64-bit PowerPC will remain the small code model. We plan to eventually change the default to medium code model, which matches current upstream GCC behavior. Note that the different code models are ABI-compatible, so code compiled with different models will be linked and execute correctly. I've tested the regression suite and the application/benchmark test suite in two ways: Once with the patch as submitted here, and once with additional logic to force medium code model as the default. The tests all compile cleanly, with one exception. The mandel-2 application test fails due to an unrelated ABI compatibility with passing complex numbers. It just so happens that small code model was incredibly lucky, in that temporary values in floating-point registers held the expected values needed by the external library routine that was called incorrectly. My current thought is to correct the ABI problems with _Complex before making medium code model the default, to avoid introducing this "regression." Here are a few comments on how the patch works, since the selection code can be difficult to follow: The existing logic for small code model defines three pseudo-instructions: LDtoc for most uses, LDtocJTI for jump table addresses, and LDtocCPT for constant pool addresses. These are expanded by SelectCodeCommon(). The pseudo-instruction approach doesn't work for medium code model, because we need to generate two instructions when we match the same pattern. Instead, new logic in PPCDAGToDAGISel::Select() intercepts the TOC_ENTRY node for medium code model, and generates an ADDIStocHA followed by either a LDtocL or an ADDItocL. These new node types correspond naturally to the sequences described above. The addis/ld sequence is generated for the following cases: * Jump table addresses * Function addresses * External global variables * Tentative definitions of global variables (common linkage) The addis/addi sequence is generated for the following cases: * Constant pool entries * File-scope static global variables * Function-scope static variables Expanding to the two-instruction sequences at select time exposes the instructions to subsequent optimization, particularly scheduling. The rest of the processing occurs at assembly time, in PPCAsmPrinter::EmitInstruction. Each of the instructions is converted to a "real" PowerPC instruction. When a TOC entry needs to be created, this is done here in the same manner as for the existing LDtoc, LDtocJTI, and LDtocCPT pseudo-instructions (I factored out a new routine to handle this). I had originally thought that if a TOC entry was needed for LDtocL or ADDItocL, it would already have been generated for the previous ADDIStocHA. However, at higher optimization levels, the ADDIStocHA may appear in a different block, which may be assembled textually following the block containing the LDtocL or ADDItocL. So it is necessary to include the possibility of creating a new TOC entry for those two instructions. Note that for LDtocL, we generate a new form of LD called LDrs. This allows specifying the @toc@l relocation for the offset field of the LD instruction (i.e., the offset is replaced by a SymbolLo relocation). When the peephole optimization described above is added, we will need to do similar things for all immediate-form load and store operations. The seven "mcm-n.ll" test cases are kept separate because otherwise the intermingling of various TOC entries and so forth makes the tests fragile and hard to understand. The above assumes use of an external assembler. For use of the integrated assembler, new relocations are added and used by PPCELFObjectWriter. Testing is done with "mcm-obj.ll", which tests for proper generation of the various relocations for the same sequences tested with the external assembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168708 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-27Remove the dependent libraries feature.Bill Wendling
The dependent libraries feature was never used and has bit-rotted. Remove it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168694 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-27[arm fast-isel] Appease the machine verifier by using the proper registerChad Rosier
classes. The associated test case still doesn't pass, but it does have far fewer issues. rdar://12719844 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168657 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-26Make aligning by 2**4 dependent on NaCl for Mips.David Sehr
Also, make emission of mips16/nomips16 not dependent on NaCl. BUG= http://code.google.com/p/nativeclient/issues/detail?id=1711 Review URL: https://codereview.chromium.org/11308210
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