emscripten-fastcomp - LLVM with the emscripten fastcomp javascript backend

Age	Commit message (Expand)	Author
2013-05-05	[XCore] Remove '-' from back branch asm syntax.	Richard Osborne
2013-05-04	[XCore] Make use of the target independent global address offset folding.	Richard Osborne
2013-04-04	[XCore] The RRegs register class is a superset of GRRegs.	Richard Osborne
2013-02-17	[XCore] Add missing 2r instructions.	Richard Osborne
2013-02-17	[XCore] Add TSETR instruction.	Richard Osborne
2013-01-27	[XCore] Add missing l2rus instructions.	Richard Osborne
2013-01-25	Add instruction encodings / disassembly support for l4r instructions.	Richard Osborne
2013-01-25	Use the correct format in the STW / SETPSC instruction names.	Richard Osborne
2013-01-25	Add instruction encodings / disassembly support for l5r instructions.	Richard Osborne
2013-01-23	Add instruction encodings / disassembly support for l6r instructions.	Richard Osborne
2013-01-21	Add instruction encoding / disassembly support for ru6 / lru6 instructions.	Richard Osborne
2013-01-20	Add instruction encodings / disassembly support for l2rus instructions.	Richard Osborne
2013-01-20	Add instruction encodings / disassembly support for l3r instructions.	Richard Osborne
2013-01-20	Add instruction encodings / disassembler support for 2rus instructions.	Richard Osborne
2013-01-20	Add instruction encodings / disassembly support 3r instructions.	Richard Osborne
2012-12-17	Add instruction encodings / disassembly support for l2r instructions.	Richard Osborne
2012-12-17	Fix parameter name in prototypes in XCoreDisassembler.	Richard Osborne
2012-12-17	Add instruction encodings / disassembly support for rus instructions.	Richard Osborne
2012-12-17	Add instruction encodings / disassembly support for 2r instructions.	Richard Osborne
2012-12-17	Update comments to match recommended doxygen style.	Richard Osborne
2012-12-16	Add instruction encodings and disassembly for 1r instructions.	Richard Osborne
2012-12-16	Add XCore disassembler.	Richard Osborne