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2012-07-18X86: remove redundant cmp against zero.Manman Ren
Updated OptimizeCompare in peephole to remove redundant cmp against zero. We only remove Compare if CF and OF are not used. rdar://11855129 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160454 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-18This patch fixes 8 out of 20 unexpected failures in "make check"Preston Gurd
when run on an Intel Atom processor. The failures have arisen due to changes elsewhere in the trunk over the past 8 weeks or so. These failures were not detected by the Atom buildbot because the CPU on the Atom buildbot was not being detected as an Atom CPU. The fix for this problem is in Host.cpp and X86Subtarget.cpp, but shall remain commented out until the current set of Atom test failures are fixed. Patch by Andy Zhang and Tyler Nowicki! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160451 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-18The vbroadcast family of instructions has 'fallback patterns' in case where theNadav Rotem
load source operand is used by multiple nodes. The v2i64 broadcast was emulated by shuffling the two lower i32 elements to the upper two. We had a bug in the immediate used for the broadcast. Replacing 0 to 0x44. 0x44 means [01|00|01|00] which corresponds to the correct lane. Patch by Michael Kuperstein. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160430 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-18Remove tab characters.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160425 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-18Fix typo in error message and remove some tab characters.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160423 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-18Make x86 asm parser to check for xmm vs ymm for index register in gather ↵Craig Topper
instructions. Also fix Intel syntax for gather instructions to use 'DWORD PTR' or 'QWORD PTR' to match gas. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160420 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-17Back out r160101 and instead implement a dag combine to recover from ↵Evan Cheng
instcombine transformation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160387 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-17Implement r160312 as target indepedenet dag combine.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160354 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-17This is another case where instcombine demanded bits optimization createdEvan Cheng
large immediates. Add dag combine logic to recover in case the large immediates doesn't fit in cmp immediate operand field. int foo(unsigned long l) { return (l>> 47) == 1; } we produce %shr.mask = and i64 %l, -140737488355328 %cmp = icmp eq i64 %shr.mask, 140737488355328 %conv = zext i1 %cmp to i32 ret i32 %conv which codegens to movq $0xffff800000000000,%rax andq %rdi,%rax movq $0x0000800000000000,%rcx cmpq %rcx,%rax sete %al movzbl %al,%eax ret TargetLowering::SimplifySetCC would transform (X & -256) == 256 -> (X >> 8) == 1 if the immediate fails the isLegalICmpImmediate() test. For x86, that's immediates which are not a signed 32-bit immediate. Based on a patch by Eli Friedman. PR10328 rdar://9758774 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160346 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16For something likeEvan Cheng
uint32_t hi(uint64_t res) { uint_32t hi = res >> 32; return !hi; } llvm IR looks like this: define i32 @hi(i64 %res) nounwind uwtable ssp { entry: %lnot = icmp ult i64 %res, 4294967296 %lnot.ext = zext i1 %lnot to i32 ret i32 %lnot.ext } The optimizer has optimize away the right shift and truncate but the resulting constant is too large to fit in the 32-bit immediate field. The resulting x86 code is worse as a result: movabsq $4294967296, %rax ## imm = 0x100000000 cmpq %rax, %rdi sbbl %eax, %eax andl $1, %eax This patch teaches the x86 lowering code to handle ult against a large immediate with trailing zeros. It will issue a right shift and a truncate followed by a comparison against a shifted immediate. shrq $32, %rdi testl %edi, %edi sete %al movzbl %al, %eax It also handles a ugt comparison against a large immediate with trailing bits set. i.e. X > 0x0ffffffff -> (X >> 32) >= 1 rdar://11866926 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160312 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16With r160248 in place this code is no longer needed.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160293 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16Fix a bug in the 3-address conversion of LEA when one of the operands is anNadav Rotem
undef virtual register. The problem is that ProcessImplicitDefs removes the definition of the register and marks all uses as undef. If we lose the undef marker then we get a register which has no def, is not marked as undef. The live interval analysis does not collect information for these virtual registers and we crash in later passes. Together with Michael Kuperstein <michael.m.kuperstein@intel.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160260 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16This CL changes the function prologue and epilogue emitted on X86 when stack ↵Alexey Samsonov
needs realignment. It is intended to fix PR11468. Old prologue and epilogue looked like this: push %rbp mov %rsp, %rbp and $alignment, %rsp push %r14 push %r15 ... pop %r15 pop %r14 mov %rbp, %rsp pop %rbp The problem was to reference the locations of callee-saved registers in exception handling: locations of callee-saved had to be re-calculated regarding the stack alignment operation. It would take some effort to implement this in LLVM, as currently MachineLocation can only have the form "Register + Offset". Funciton prologue and epilogue are now changed to: push %rbp mov %rsp, %rbp push %14 push %15 and $alignment, %rsp ... lea -$size_of_saved_registers(%rbp), %rsp pop %r15 pop %r14 pop %rbp Reviewed by Chad Rosier. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160248 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-15Teach getTargetVShiftNode about TargetConstant nodes.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160234 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-15Rename VBROADCASTSDrm into VBROADCASTSDYrm to match the naming convention.Nadav Rotem
Allow the folding of vbroadcastRR to vbroadcastRM, where the memory operand is a spill slot. PR12782. Together with Michael Kuperstein <michael.m.kuperstein@intel.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160230 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-14AVX: Fix a bug in getTargetVShiftNode. The shift amount has to be a 128bit ↵Nadav Rotem
vector with the same element type as the input vector. This is needed because of the patterns we have for the VP[SLL/SRA/SRL][W/D/Q] instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160222 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-13Make helper functions static.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160173 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-13Mark VINSERTI128rm as MayLoad=1. Fixes PR13348.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160162 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-12Give the rdrand instructions a SideEffect flag and a chain so MachineCSE and ↵Benjamin Kramer
MachineLICM don't touch it. I already had the necessary things in place for IR-level passes but missed the machine passes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160137 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-12Add intrinsics for Ivy Bridge's rdrand instruction.Benjamin Kramer
The rdrand/cmov sequence is the same that is emitted by both GCC and ICC. Fixes PR13284. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160117 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-12Update GATHER instructions to support 2 read-write operands. Patch from ↵Craig Topper
myself and Manman Ren. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160110 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-11[x86 fast-isel] Per discussion with Eric, add all cases to switch with verboseChad Rosier
comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160069 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-11X86: Update to peephole optimization to move Movr0 before (Sub, Cmp) pair.Manman Ren
When Movr0 is between sub and cmp, we move Movr0 before sub if it enables removal of Cmp. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160066 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-11[x86 fast-isel] Rather then call llvm_unreachable() have fast-isel fall backChad Rosier
to Selection DAG isel. Patch by Andrew Kaylor <andrew.kaylor@intel.com>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160055 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-11When ext-loading and trunc-storing vectors to memory, on x86 32bit systems, ↵Nadav Rotem
allow loads/stores of 64bit values from xmm registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160044 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10Move [get|set]BasePtrStackAdjustment() from MachineFrameInfo toChad Rosier
X86MachineFunctionInfo as this is currently only used by X86. If this ever becomes an issue on another arch (e.g., ARM) then we can hoist it back out. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160009 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10Add support for dynamic stack realignment in the presence of dynamic allocas onChad Rosier
X86. Basically, this is a reapplication of r158087 with a few fixes. Specifically, (1) the stack pointer is restored from the base pointer before popping callee-saved registers and (2) in obscure cases (see comments in patch) we must cache the value of the original stack adjustment in the prologue and apply it in the epilogue. rdar://11496434 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160002 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10Add back an unrelated bit of code that exists upstream but not here.Derek Schuff
TBR BUG=http://code.google.com/p/nativeclient/issues/detail?id=2295 TEST=none Review URL: https://chromiumcodereview.appspot.com/10702127 Change-Id: Id04643554eb0a4ad3f31df5f13f5fcb7ce5aff71
2012-07-10Improve the loading of load-anyext vectors by allowing the codegen to loadNadav Rotem
multiple scalars and insert them into a vector. Next, we shuffle the elements into the correct places, as before. Also fix a small dagcombine bug in SimplifyBinOpWithSameOpcodeHands, when the migration of bitcasts happened too late in the SelectionDAG process. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159991 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-10Reverse assembler/disassembler operand order for gather instructions.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159983 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-09X86: implement functions to analyze & synthesize CMOV|SET|JccManman Ren
getCondFromSETOpc, getCondFromCMovOpc, getSETFromCond, getCMovFromCond No functional change intended. If we want to update the condition code of CMOV|SET|Jcc, we first analyze the opcode to get the condition code, then update the condition code, finally synthesize the new opcode form the new condition code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159955 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-09LOCALMODs from hg 0b098ca44de7 against r158408 (hg 90a87d6bfe45)Derek Schuff
(only non-new files; new files in git 4f429c8b) Change-Id: Ia39f818088485bd90e4d048db404f8d6ba5f836b
2012-07-07I'm introducing a new machine model to simultaneously allow simpleAndrew Trick
subtarget CPU descriptions and support new features of MachineScheduler. MachineModel has three categories of data: 1) Basic properties for coarse grained instruction cost model. 2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD). 3) Instruction itineraties for detailed per-cycle reservation tables. These will all live side-by-side. Any subtarget can use any combination of them. Instruction itineraries will not change in the near term. In the long run, I expect them to only be relevant for in-order VLIW machines that have complex contraints and require a precise scheduling/bundling model. Once itineraries are only actively used by VLIW-ish targets, they could be replaced by something more appropriate for those targets. This tablegen backend rewrite sets things up for introducing MachineModel type #2: per opcode/operand cost model. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159891 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-07X86: Fix optimizeCompare to correctly check safe condition.Manman Ren
It is safe if EFLAGS is killed or re-defined. When we are done with the basic block, check whether EFLAGS is live-out. Do not optimize away cmp if EFLAGS is live-out. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159888 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-06X86: peephole optimization to remove cmp instructionManman Ren
For each Cmp, we check whether there is an earlier Sub which make Cmp redundant. We handle the case where SUB operates on the same source operands as Cmp, including the case where the two source operands are swapped. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159838 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-04Make X86 call and return instructions non-variadic.Jakob Stoklund Olesen
Function argument and return value registers aren't part of the encoding, so they should be implicit operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159728 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-04Ensure CopyToReg nodes are always glued to the call instruction.Jakob Stoklund Olesen
The CopyToReg nodes that set up the argument registers before a call must be glued to the call instruction. Otherwise, the scheduler may emit the physreg copies long before the call, causing long live ranges for the fixed registers. Besides disabling good register allocation, that can also expose problems when EmitInstrWithCustomInserter() splits a basic block during the live range of a physreg. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159721 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-04Add early if-conversion support to X86.Jakob Stoklund Olesen
Implement the TII hooks needed by EarlyIfConversion to create cmov instructions and estimate their latency. Early if-conversion is still not enabled by default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159695 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-03Diff from hg rev 0b098ca44de7Derek Schuff
2012-07-03Remove extra space.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159647 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-03Change i128mem/i256mem to f128mem/f256mem on some floating point vector ↵Craig Topper
instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159646 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-03Add aliases for pblendvb, blendvpd, and blendvps instructions with the ↵Craig Topper
implicit xmm0 operand specified. Fixes PR13252. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159644 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-02Add all codegen passes to the PassManager via TargetPassConfig.Bob Wilson
This is a preliminary step toward having TargetPassConfig be able to start and stop the compilation at specified passes for unit testing and debugging. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159567 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-01Optimization of shuffle node that can fit to the register form of VBROADCAST ↵Elena Demikhovsky
instruction on AVX2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159504 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-01Reduce code size by using a second switch statement to avoid extra calls to ↵Craig Topper
SelectAtomic64. Also catch cases where SelectAtomic64 fails. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159503 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-01Add a break to the end of case statement missed in r159501.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159502 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-01Fix a crash on release builds if gather intrinsics are passed a non-constant ↵Craig Topper
value for the last argument. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159501 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-01Use a second switch statement to reduce number of calls to SelectGather in ↵Craig Topper
code. Reduces code size a bit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159500 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-29In the initial exec mode we always do a load to find the address of a variable.Rafael Espindola
Before this patch in pic 32 bit code we would add the global base register and not load from that address. This is a really old bug, but before the introduction of the tls attributes we would never select initial exec for pic code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159409 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-29X86: add more GATHER intrinsics in LLVMManman Ren
Corrected type for index of llvm.x86.avx2.gather.d.pd.256 from 256-bit to 128-bit. Corrected types for src|dst|mask of llvm.x86.avx2.gather.q.ps.256 from 256-bit to 128-bit. Support the following intrinsics: llvm.x86.avx2.gather.d.q, llvm.x86.avx2.gather.q.q llvm.x86.avx2.gather.d.q.256, llvm.x86.avx2.gather.q.q.256 llvm.x86.avx2.gather.d.d, llvm.x86.avx2.gather.q.d llvm.x86.avx2.gather.d.d.256, llvm.x86.avx2.gather.q.d.256 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159402 91177308-0d34-0410-b5e6-96231b3b80d8
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