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2012-08-05Remove custom inserter for MWAIT. It doesn't do anything that couldn't be ↵Craig Topper
represented in a pattern. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161306 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-05Use a COPY node instead of an explicit MOVA opcode in the custom insterter ↵Craig Topper
for pcmpestrm/pcmpistrm. Allows the register allocator to handle it better and prevent wasted identity moves. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161305 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-03Fall back to selection DAG isel for calls to builtin functions.Bob Wilson
Fast isel doesn't currently have support for translating builtin function calls to target instructions. For embedded environments where the library functions are not available, this is a matter of correctness and not just optimization. Most of this patch is just arranging to make the TargetLibraryInfo available in fast isel. <rdar://problem/12008746> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161232 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-02X86 Peephole: fold loads to the source register operand if possible.Manman Ren
Add more comments and use early returns to reduce nesting in isLoadFoldable. Also disable folding for V_SET0 to avoid introducing a const pool entry and a const pool load. rdar://10554090 and rdar://11873276 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161207 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-02X86 Peephole: fold loads to the source register operand if possible.Manman Ren
Machine CSE and other optimizations can remove instructions so folding is possible at peephole while not possible at ISel. This patch is a rework of r160919 and was tested on clang self-host on my local machine. rdar://10554090 and rdar://11873276 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161152 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-01X86: mark GATHER instructios as mayLoadManman Ren
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161143 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-01Whitespace.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161122 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-01Added FMA functionality to X86 target.Elena Demikhovsky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161110 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-01Add more indirection to the disassembler tables to reduce amount of space ↵Craig Topper
used to store the operand types and encodings. Store only the unique combinations in a separate table and store indices in the instruction table. Saves about 32K of static data. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161101 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-31remove superfluous addr32 prefix bytes for zero-based sandboxAustin Benson
BUG=http://code.google.com/p/nativeclient/issues/detail?id=2927 TEST=spec2k Review URL: http://codereview.chromium.org/10834024/
2012-07-31Restrict R15 with a flagAustin Benson
http://codereview.chromium.org/10820013/
2012-07-31Fix cases where fast instruction selection generated both base and indexKarl Schimpf
registers. BUG= http://code.google.com/p/nativeclient/issues/detail?id=2544 Review URL: http://chromiumcodereview.appspot.com/10808110
2012-07-31Add dst-only naclrest, nacljmpAustin Benson
Review URL: http://codereview.chromium.org/10806068/
2012-07-31clean up handling of sandbox memory references for x86-64Austin Benson
http://codereview.chromium.org/10803038/
2012-07-31Add sfi-zero-based-sandbox option for zero-based sandbox model support on 64-bitAustin Benson
systems Review URL: http://codereview.chromium.org/10692083/
2012-07-31[x86 frame lowering] In 32-bit mode, use ESI as the base pointer.Chad Rosier
Previously, we were using EBX, but PIC requires the GOT to be in EBX before function calls via PLT GOT pointer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161066 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-31Make INSTRUCTION_SPECIFIER_FIELDS match X86DisassemblerCommon.h. Also remove ↵Craig Topper
trailing whitespace. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161029 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-31Tidy up trailing whitespaceCraig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161027 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-31Tidy up trailing whitespaceCraig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161026 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-30Mark MOVZX16/MOVSX16 as neverHasSideEffects/mayLoadCraig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160953 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-30Mark MOVZX32_NOREX as isCodeGenOnly and neverHasSideEffects. The ↵Craig Topper
isCodeGenOnly change allows special detection of _NOREX instructions to be removed from tablegen disassembler code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160951 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-30Give VCVTTPD2DQ priority over CVTTPD2DQ.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160942 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-30Fix patterns for CVTTPS2DQ to specify SSE2 instead of SSE1.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160941 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-30Fix up patterns for VCVTSS2SD. Specifically give it priority over SSE form. ↵Craig Topper
Add an OptForSpeed to explicitly pair up with an OptForSize that was already on another pattern. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160939 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-29Fix load types on intrinsic forms of SS2SD and SD2SS AVX/SSE convert ↵Craig Topper
instruction patterns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160938 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-29Move more SSE/AVX convert instruction patterns into their definitions.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160937 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-29Revert r160920 and r160919 due to dragonegg and clang selfhost failureManman Ren
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160927 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-28Fold patterns for some of the SSE/AVX convert instructions into their ↵Craig Topper
instruction definitions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160922 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-28Mark some of the SSE/AVX convert instructions as mayLoad/neverHasSideEffects.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160921 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-28X86 Peephole: fold loads to the source register operand if possible.Manman Ren
Machine CSE and other optimizations can remove instructions so folding is possible at peephole while not possible at ISel. rdar://10554090 and rdar://11873276 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160919 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-28Make CVTSS2SI instruction definition consistent with CVTSD2SI.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160914 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-28Fix up memory load types for SSE scalar convert intrinsic patterns.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160913 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-28X86 Peephole: fix PR13475 in optimizeCompare.Manman Ren
It is possible that an instruction can use and update EFLAGS. When checking the safety, we should check the usage of EFLAGS first before declaring it is safe to optimize due to the update. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160912 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-26Remove the X86 sub_ss and sub_sd sub-register indexes completely.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160833 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-26Remove the last mentions of sub_ss and sub_sd from patterns.Jakob Stoklund Olesen
I'll remove these two sub-register indexes shortly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160831 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-26Eliminate sub_ss, sub_sd from broadcast patterns.Jakob Stoklund Olesen
The (COPY_TO_REGCLASS GR32:$src, VR128) pattern looks odd, but copyPhysReg does the right thing with it. (The old pattern would eventually produce the same cross-class copy). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160830 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-26Eliminate more sub_ss / sub_sd patterns.Jakob Stoklund Olesen
This gets rid of some more INSERT_SUBREG - IMPLICIT_DEF patterns, simplifying the emitted code a bit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160820 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-26Eliminate some SUBREG_TO_REG patterns with sub_ss and sub_sd.Jakob Stoklund Olesen
The SUBREG_TO_REG instruction has magic semantics asserting that the source value was defined by an instruction that cleared the high half of the register. Those semantics are never actually exploited for xmm registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160818 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-26Eliminate a batch of uses of sub_ss and sub_sd in the X86 target.Jakob Stoklund Olesen
These idempotent sub-register indices don't do anything --- They simply map XMM registers to themselves. They no longer affect register classes either since the SubRegClasses field has been removed from Target.td. This patch replaces XMM->XMM EXTRACT_SUBREG and INSERT_SUBREG patterns with COPY_TO_REGCLASS patterns which simply become COPY instructions. The number of IMPLICIT_DEF instructions before register allocation is reduced, and that is the cause of the test case changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160816 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-26Make l/q suffixes on AVX forms of scalar convert instructions consistent ↵Craig Topper
with their non-AVX forms. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160775 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-25Fix typos. Thanks to Matt Beaumont-Gay for noticing it.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160731 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-25When a return struct pointer is passed in registers, the called has nothingRafael Espindola
to pop. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160725 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-25Factor a long list of conditions into a predicate function. No functionalityRafael Espindola
change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160724 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-24Fix a bug in the x86 disassembler's symbolic disassembly support for Jcc-JumpKevin Enderby
if Condition Is Met instuctions that was not correctly determining the target instruction. So for a jne rel32 instruction: % cat x.s .byte 0x0f, 0x85, 0x09, 0x00, 0x00, 0x00 % as x.s it was incorrectly deterining the target: % otool -q -tv a.out a.out: (__TEXT,__text) section 0000000000000000 jne 0xd and with the fix it gets this correct as: % otool -q -tv a.out a.out: (__TEXT,__text) section 0000000000000000 jne 0xf rdar://11505997 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160694 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-24ELF does not imply GNU/Linux. Do not assume GNU conventions just because weDavid Chisnall
are targeting an ELF platform. Only fold gs-relative (and fs-relative) loads if it is actually sensible to do so for the target platform. This fixes PR13438. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160687 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-23Fix a typo (the the => the)Sylvestre Ledru
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160621 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-20Don't use implicit register operands to calculate L-bit for AVX ↵Craig Topper
instructions. Needed because super reg defs and kills are added as implicit operands on 128-bit instructions. Fixes PR13349. Patch by Jose Fonseca. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160543 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-19Adds the family codes for the Midview Atom processors so that thePreston Gurd
Atom buildbot will auto-detect Atom. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160521 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-19Remove tabs.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160479 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-19Remove tabs.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160477 91177308-0d34-0410-b5e6-96231b3b80d8
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