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2012-10-29Fix PR14204Michael Liao
- Add missing pattern on X86ISD::VZEXT from VR256 to VR256 when AVX2 is enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166947 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-29Fix typoJoerg Sonnenberger
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166945 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-29Make sret register classes match for llc at -O0.Jan Voung
PointerTy() is i32, so we end up with EDI as the sret register. However, this means that the copy to RAX won't match. We could either copy to EAX to have the register classes match, or promote EDI to RDI then copy. It shouldn't matter much since only the lower 32-bits matter. The EDI -> EAX version is 2 bytes while the the RDI -> RAX version is 3 bytes, so let's pick the smaller one. Also augment existing test to tickle the NaCl triple. This is mostly to get the debugger test working (since the debugger test fails when optimization is turned on). BUG= http://code.google.com/p/nativeclient/issues/detail?id=3104 BUG= http://code.google.com/p/nativeclient/issues/detail?id=2544 TEST= ./scons bitcode=1 platform=x86-64 run_gdb_change_variable_test (with a hacked driver that use -O0 for llc) TEST= test/CodeGen/X86/fast-isel-x86-64.ll Review URL: https://codereview.chromium.org/11308022
2012-10-29Silence a GCC warning about comparing signed and unsigned types.Duncan Sands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166922 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-28Remove TargetELFWriterInfo.Rafael Espindola
All the credit goes to Jan Voung for noticing it was dead! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166902 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-26[ms-inline asm] Add a comment.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166819 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-26[ms-inline asm] Emit an error for unsupported SIZE and LENGTH directives.Chad Rosier
Part of rdar://12576868 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166792 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-26[ms-inline asm] Add support for the TYPE operator.Chad Rosier
Part of rdar://12576868 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166790 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-26[ms-inline asm] Have the target AsmParser create the asmrewrite for the offsetofChad Rosier
operator. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166779 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-25[ms-inline asm] Perform field lookups with the dot operator.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166724 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-25[ms-inline asm] Add support for creating AsmRewrites in the target specificChad Rosier
AsmParser logic. To be used/tested in a subsequent commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166714 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-25Merge commit 'a8a0a155de16830b8fcab539ba2ec21de3145532'Derek Schuff
Conflicts: lib/Target/X86/X86FrameLowering.cpp lib/Target/X86/X86ISelLowering.cpp The Intel folks switched some of the FrameLowering code to use X86RegisterInfo::getSlotSize isntead of pointer size, thus reducing our localmods in that file.
2012-10-25[ms-inline asm] Add error handling to the ParseIntelDotOperator() function.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166698 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-25Atom has SIMD instruction set extension up to SSSE3Michael Liao
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166665 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-25Clean up where SlotSize should be used instead of pointer size.Michael Liao
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166664 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-24[ms-inline asm] Add support for parsing the '.' operator. Given,Chad Rosier
[register].field The operator returns the value at the location pointed to by register plus the offset of field within its structure or union. This patch only handles immediate fields (i.e., [eax].4). The original displacement has to be a MCConstantExpr as well. Part of rdar://12470415 and rdar://12470514 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166632 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-24Tidy up. No functional change intended.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166630 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-24Implement a basic VectorTargetTransformInfo interface to be used by the loop ↵Nadav Rotem
and bb vectorizers for modeling the cost of instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166593 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-24[ms-inline asm] Create a register operand, rather than a memory operand when weChad Rosier
see the offsetof operator. Previously, we were matching something like MOVrm in the front-end and later matching MOVrr in the back-end. This change makes things more consistent. It also fixes cases where we can't match against a memory operand as the source (test cases coming). Part of rdar://12470317 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166592 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-24Add in support for getIntPtrType to get the pointer type based on the ↵Micah Villmow
address space. This checkin also adds in some tests that utilize these paths and updates some of the clients. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166578 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-24Special calling conventions for Intel OpenCL built-in library.Elena Demikhovsky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166566 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-24Add custom conversion from v2u32 to v2f32 in 32-bit modeMichael Liao
- As there's no 64-bit GPRs in 32-bit mode, a custom conversion from v2u32 to v2f32 is added to improve the efficiency of the code generated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166545 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-24Change x86_fastcallcc to require inreg markers. This allows it to knownRafael Espindola
the difference from "int x" (which should go in registers and "struct y {int x;}" (which should not). Clang will be updated in the next patches. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166536 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-23[ms-inline asm] Offset operator - the size should be based on the size of aChad Rosier
pointer, not the size of the variable. Part of rdar://12470317 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166526 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-23[ms-inline asm] Clean up comment.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166525 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-23[ms-inline asm] When parsing inline assembly we set the base register to aChad Rosier
non-zero value as we don't know the actual value at this point. This is necessary to get the matching correct in some cases. However, the actual value set as the base register doesn't matter, since we're just matching not emitting. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166523 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-23Make branch heavy code for generating marked up disassembly simplerKevin Enderby
and easier to read by adding a couple helper functions. Suggestion by Chandler Carruth and seconded by Meador Inge! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166515 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-23Fix PR14161Michael Liao
- Check index being extracted to be constant 0 before simplfiying. Otherwise, retain the original sequence. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166504 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-23Silence -Wsign-compareMatt Beaumont-Gay
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166494 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-23Merge commit '92b0d8cf2c51debc7f4fb30a417ae839077a8ed0'Derek Schuff
Conflicts: lib/Target/ARM/ARMISelLowering.cpp lib/Target/Mips/MipsISelLowering.h lib/Target/X86/X86ISelLowering.h lib/Target/X86/X86TargetMachine.h tools/llc/llc.cpp The only interesting conflict was ARMISelLowering, caused by http://llvm.org/viewvc/llvm-project?view=rev&revision=166273 which actually removes a LOCALMOD for ARM byval lowering.
2012-10-23[ms-inline asm] Add an implementation of the offset operator. This is a followChad Rosier
on patch to r166433. rdar://12470317 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166488 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-23Add custom UINT_TO_FP from v4i8/v4i16/v8i8/v8i16 to v4f32/v8f32Michael Liao
- Replace v4i8/v8i8 -> v8f32 DAG combine with custom lowering to reduce DAG combine overhead. - Extend the support to v4i16/v8i16 as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166487 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-23Enable lowering ZERO_EXTEND/ANY_EXTEND to PMOVZX from SSE4.1Michael Liao
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166486 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-22Add support for annotated disassembly output for X86 and arm.Kevin Enderby
Per the October 12, 2012 Proposal for annotated disassembly output sent out by Jim Grosbach this set of changes implements this for X86 and arm. The llvm-mc tool now has a -mdis option to produced the marked up disassembly and a couple of small example test cases have been added. rdar://11764962 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166445 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-22[ms-inline asm] Add the isOffsetOf() function.Chad Rosier
Part of rdar://12470317 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166436 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-22[ms-inline asm] Add support for parsing the offset operator. Callback for Chad Rosier
CodeGen in the front-end not implemented yet. rdar://12470317 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166433 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-19[ms-inline asm] Reset the opcode prior to parsing a statement.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166349 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-19[ms-inline asm] Have the TargetParser callback to Sema to determine the size ofChad Rosier
a memory operand. Retain this information and then add the sizing directives to the IR. This allows the backend to do proper instruction selection. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166316 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-19This patch is to fix radar://8426430. It is about llvm support of ↵Shuxin Yang
__builtin_debugtrap() which is supposed to consistently raise SIGTRAP across all systems. In contrast, __builtin_trap() behave differently on different systems. e.g. it raises SIGTRAP on ARM, and SIGILL on X86. The purpose of __builtin_debugtrap() is to consistently provide "trap" functionality, in the mean time preserve the compatibility with on gcc on __builtin_trap(). The X86 backend is already able to handle debugtrap(). This patch is to: 1) make front-end recognize "__builtin_debugtrap()" (emboddied in the one-line change to Clang). 2) In DAG legalization phase, by default, "debugtrap" will be replaced with "trap", which make the __builtin_debugtrap() "available" to all existing ports without the hassle of changing their code. 3) If trap-function is specified (via -trap-func=xyz to llc), both __builtin_debugtrap() and __builtin_trap() will be expanded into the function call of the specified trap function. This behavior may need change in the future. The provided testing-case is to make sure 2) and 3) are working for ARM port, and we already have a testing case for x86. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166300 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-19Lower BUILD_VECTOR to SHUFFLE + INSERT_VECTOR_ELT for X86Michael Liao
- If INSERT_VECTOR_ELT is supported (above SSE2, either by custom sequence of legal insn), transform BUILD_VECTOR into SHUFFLE + INSERT_VECTOR_ELT if most of elements could be built from SHUFFLE with few (so far 1) elements being inserted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166288 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-18Reapply the TargerTransformInfo changes, minus the changes to LSR and ↵Nadav Rotem
Lowerinvoke. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166248 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-18Merge commit '3298959540ca744ec16b4c65db244534a929a862'Derek Schuff
Conflicts: lib/Target/X86/X86TargetMachine.h tools/llc/llc.cpp
2012-10-18support X86::RETI in 64-bit modeDavid Sehr
BUG= http://code.google.com/p/nativeclient/issues/detail?id=2801 TEST=none Review URL: https://codereview.chromium.org/11198043
2012-10-18Temporarily revert the TargetTransform changes.Bob Wilson
The TargetTransform changes are breaking LTO bootstraps of clang. I am working with Nadav to figure out the problem, but I am reverting it for now to get our buildbots working. This reverts svn commits: 165665 165669 165670 165786 165787 165997 and I have also reverted clang svn 165741 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166168 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-17Check for empty YMM use-def lists in X86VZeroUpper.Jakob Stoklund Olesen
The previous MRI.isPhysRegUsed(YMM0) would also return true when the function contains a call to a function that may clobber YMM0. That's most of them. Checking the use-def chains allows us to skip functions that don't explicitly mention YMM registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166110 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-17Check SSSE3 instead of SSE4.1Michael Liao
- All shuffle insns required, especially PSHUB, are added in SSSE3. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166086 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-17Fix setjmp on models with non-Small code model nor non-Static relocation modelMichael Liao
- MBB address is only valid as an immediate value in Small & Static code/relocation models. On other models, LEA is needed to load IP address of the restore MBB. - A minor fix of MBB in MC lowering is added as well to enable target relocation flag being propagated into MC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166084 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-16Merge commit '320db3f8052c9f506d9ea043ba5da534df40aa08'Derek Schuff
2012-10-16Support v8f32 to v8i8/vi816 conversion through custom loweringMichael Liao
- Add custom FP_TO_SINT on v8i16 (and v8i8 which is legalized as v8i16 due to vector element-wise widening) to reduce DAG combiner and its overhead added in X86 backend. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166036 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-16Reapply r165661, Patch by Shuxin Yang <shuxin.llvm@gmail.com>.NAKAMURA Takumi
Original message: The attached is the fix to radar://11663049. The optimization can be outlined by following rules: (select (x != c), e, c) -> select (x != c), e, x), (select (x == c), c, e) -> select (x == c), x, e) where the <c> is an integer constant. The reason for this change is that : on x86, conditional-move-from-constant needs two instructions; however, conditional-move-from-register need only one instruction. While the LowerSELECT() sounds to be the most convenient place for this optimization, it turns out to be a bad place. The reason is that by replacing the constant <c> with a symbolic value, it obscure some instruction-combining opportunities which would otherwise be very easy to spot. For that reason, I have to postpone the change to last instruction-combining phase. The change passes the test of "make check-all -C <build-root/test" and "make -C project/test-suite/SingleSource". Original message since r165661: My previous change has a bug: I negated the condition code of a CMOV, and go ahead creating a new CMOV using the *ORIGINAL* condition code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166017 91177308-0d34-0410-b5e6-96231b3b80d8
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