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bytes.
The stack realignment code was fixed to work when there is stack realignment and
a dynamic alloca is present so this shouldn't cause correctness issues anymore.
Note that this also enables generation of AVX instructions for memset
under the assumptions:
- Unaligned loads/stores are always fast on CPUs supporting AVX
- AVX is not slower than SSE
We may need some tweaked heuristics if one of those assumptions turns out not to
be true.
Effectively reverts r58317. Part of PR2962.
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When an instruction as written requires 32-bit mode and we're assembling
in 64-bit mode, or vice-versa, issue a more specific diagnostic about
what's wrong.
rdar://12700702
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predicates.
R=dschuff@chromium.org
Review URL: https://codereview.chromium.org/11361253
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Conflicts:
lib/Target/Mips/MipsISelLowering.cpp
lib/Target/X86/X86ISelLowering.cpp
lib/Target/X86/X86InstrFormats.td
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Do some cleanup of the code while here.
Inspired by patch by Logan Chien!
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chain is correctly setup.
As an example, if the original load must happen before later stores, we need
to make sure the constructed VZEXT_LOAD is constrained to be before the stores.
rdar://12684358
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- Fix operand order for atomic sub, where the minuend is the value
loaded from memory and the subtrahend is the parameter specified.
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functions static.
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reverts r126226.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167607 91177308-0d34-0410-b5e6-96231b3b80d8
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This is in preparation for adding an LLVM pass that will expand out
TLS (thread_local) variable accesses into calls to nacl.read.tp.
On ARM, there is already an arm.thread.pointer intrinsic. We reuse
the code for that.
On x86, we have to add an implementation. The added code is based on
x86's LowerToTLSExecModel() for the %gs:0 case, and on NaCl-MIPS'
LowerGlobalTLSAddress() for the __nacl_read_tp() case. (In contrast,
X86NaClRewritePass.cpp inserts a __nacl_read_tp() call at the lower MI
level; we don't use that approach here.)
We convert LowerINTRINSIC_WO_CHAIN() into a method in order to access
the Subtarget member. This is consistent with other x86 Lower methods
and with the ARM version.
BUG=https://code.google.com/p/nativeclient/issues/detail?id=2837
TEST="llvm-lit test/NaCl"
Review URL: https://codereview.chromium.org/11383002
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- Add RTM code generation support throught 3 X86 intrinsics:
xbegin()/xend() to start/end a transaction region, and xabort() to abort a
tranaction region
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Conflicts:
lib/Target/ARM/ARMFrameLowering.cpp
lib/Target/Mips/MipsRegisterInfo.cpp
lib/Target/X86/X86ISelLowering.cpp
lib/Transforms/IPO/ExtractGV.cpp
tools/Makefile
tools/gold/gold-plugin.cpp
The only interesting conflict was X86ISelLowering.ccp, which
meant I had to essentially revert r167104. The problem is that we are
using ESP as the stack pointer in X86ISelLowering and RSP as the
stack pointer in X86FrameLowering, and that revision made them
both consistently use X86RegisterInfo to determine which to use.
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for SSE4, AVX and AVX2.
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inserting/extracting from XMM registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167333 91177308-0d34-0410-b5e6-96231b3b80d8
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Reverts a LOCALMOD that incorrectly patched an upstream issue.
BUG= http://code.google.com/p/nativeclient/issues/detail?id=3110
TEST=none
Review URL: https://codereview.chromium.org/11364030
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r165941: Resubmit the changes to llvm core to update the functions to
support different pointer sizes on a per address space basis.
Despite this commit log, this change primarily changed stuff outside of
VMCore, and those changes do not carry any tests for correctness (or
even plausibility), and we have consistently found questionable or flat
out incorrect cases in these changes. Most of them are probably correct,
but we need to devise a system that makes it more clear when we have
handled the address space concerns correctly, and ideally each pass that
gets updated would receive an accompanying test case that exercises that
pass specificaly w.r.t. alternate address spaces.
However, from this commit, I have retained the new C API entry points.
Those were an orthogonal change that probably should have been split
apart, but they seem entirely good.
In several places the changes were very obvious cleanups with no actual
multiple address space code added; these I have not reverted when
I spotted them.
In a few other places there were merge conflicts due to a cleaner
solution being implemented later, often not using address spaces at all.
In those cases, I've preserved the new code which isn't address space
dependent.
This is part of my ongoing effort to clean out the partial address space
code which carries high risk and low test coverage, and not likely to be
finished before the 3.2 release looms closer. Duncan and I would both
like to see the above issues addressed before we return to these
changes.
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getIntPtrType support for multiple address spaces via a pointer type,
and also introduced a crasher bug in the constant folder reported in
PR14233.
These commits also contained several problems that should really be
addressed before they are re-committed. I have avoided reverting various
cleanups to the DataLayout APIs that are reasonable to have moving
forward in order to reduce the amount of churn, and minimize the number
of commits that were reverted. I've also manually updated merge
conflicts and manually arranged for the getIntPtrType function to stay
in DataLayout and to be defined in a plausible way after this revert.
Thanks to Duncan for working through this exact strategy with me, and
Nick Lewycky for tracking down the really annoying crasher this
triggered. (Test case to follow in its own commit.)
After discussing with Duncan extensively, and based on a note from
Micah, I'm going to continue to back out some more of the more
problematic patches in this series in order to ensure we go into the
LLVM 3.2 branch with a reasonable story here. I'll send a note to
llvmdev explaining what's going on and why.
Summary of reverted revisions:
r166634: Fix a compiler warning with an unused variable.
r166607: Add some cleanup to the DataLayout changes requested by
Chandler.
r166596: Revert "Back out r166591, not sure why this made it through
since I cancelled the command. Bleh, sorry about this!
r166591: Delete a directory that wasn't supposed to be checked in yet.
r166578: Add in support for getIntPtrType to get the pointer type based
on the address space.
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The adc/sbb optimization is to able to convert following expression
into a single adc/sbb instruction:
(ult) ... = x + 1 // where the ult is unsigned-less-than comparison
(ult) ... = x - 1
This change is to flip the "x >u y" (i.e. ugt comparison) in order
to expose the adc/sbb opportunity.
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Warnings: unused variables, unused functions, -Wreorder,
and remember to return a value in a non-void function.
Also remove setjmp/longjmp intrinsics for x86, which aren't
being used now (no equivalents in ARM and no equivalent for
x86-64 with the zero-based sandbox, etc.). This exposes a
few more unused functions.
BUG= none
TEST= test-all
Review URL: https://codereview.chromium.org/11345016
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Cameron McInally.
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the first source operand is tied to the destination operand.
This is to accurately model the corresponding instructions where the upper
bits are unmodified.
rdar://12558838
PR14221
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We used to generate a store (movq) + a load.
Now we use movd.
rdar://9946746
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to test it with chapni's fix (-mattr=+avx).
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%0 = load <8 x i16>* %dest
%1 = shufflevector <8 x i16> %0, <8 x i16> %in,
<8 x i32> < i32 0, i32 1, i32 2, i32 3, i32 13, i32 undef, i32 14, i32 14>
store <8 x i16> %1, <8 x i16>* %dest
We get:
vmovlpd (%eax), %xmm0, %xmm0
instead of:
vmovaps (%eax), %xmm1
vmovsd %xmm1, %xmm0, %xmm0
No extra test-case is added. I just fixed the existing one
(also it uses FileCheck now).
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equivalent to [expr1 + expr2]. See test cases for more examples.
rdar://12470392
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