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2012-12-11Change TargetLowering::findRepresentativeClass to take an MVT, insteadPatrik Hagglund
of EVT. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169845 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11Fall back to the selection dag isel to select tail calls.Chad Rosier
This shouldn't affect codegen for -O0 compiles as tail call markers are not emitted in unoptimized compiles. Testing with the external/internal nightly test suite reveals no change in compile time performance. Testing with -O1, -O2 and -O3 with fast-isel enabled did not cause any compile-time or execution-time failures. All tests were performed on my x86 machine. I'll monitor our arm testers to ensure no regressions occur there. In an upcoming clang patch I will be marking the objc_autoreleaseReturnValue and objc_retainAutoreleaseReturnValue as tail calls unconditionally. While it's theoretically true that this is just an optimization, it's an optimization that we very much want to happen even at -O0, or else ARC applications become substantially harder to debug. Part of rdar://12553082 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169796 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-10Some enhancements for memcpy / memset inline expansion.Evan Cheng
1. Teach it to use overlapping unaligned load / store to copy / set the trailing bytes. e.g. On 86, use two pairs of movups / movaps for 17 - 31 byte copies. 2. Use f64 for memcpy / memset on targets where i64 is not legal but f64 is. e.g. x86 and ARM. 3. When memcpy from a constant string, do *not* replace the load with a constant if it's not possible to materialize an integer immediate with a single instruction (required a new target hook: TLI.isIntImmLegal()). 4. Use unaligned load / stores more aggressively if target hooks indicates they are "fast". 5. Update ARM target hooks to use unaligned load / stores. e.g. vld1.8 / vst1.8. Also increase the threshold to something reasonable (8 for memset, 4 pairs for memcpy). This significantly improves Dhrystone, up to 50% on ARM iOS devices. rdar://12760078 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169791 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-10Revert "Make '-mtune=x86_64' assume fast unaligned memory accesses."Chandler Carruth
Accidental commit... git svn betrayed me. Sorry for the noise. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169741 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-10Make '-mtune=x86_64' assume fast unaligned memory accesses.Chandler Carruth
Summary: Not all chips targeted by x86_64 have this feature, but a dramatically increasing number do. Specifying a chip-specific tuning parameter will continue to turn the feature on or off as appropriate for that particular chip, but the generic flag should try to achieve the best performance on the most widely available hardware. Today, the number of chips with fast UA access dwarfs those without in the x86-64 space. Note that this also brings LLVM's code generation for this '-march' flag more in line with that of modern GCCs. CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D195 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169740 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-10Fix a typo in my previous commit -- bloomfield is 0x1A not 0x2A.Chandler Carruth
Thanks to the PaX folks for noticing in review! We need some tests here, any sugestions welcome... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169739 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-10Address a FIXME and update the fast unaligned memory feature for newerChandler Carruth
Intel chips. The model number rules were determined by inspecting Intel's documentation for their newer chip model numbers. My understanding is that all of the newer Intel chips have fast unaligned memory access, but if anyone is concerned about a particular chip, just shout. No tests updated; it's not clear we have dedicated tests for the chips' various features, but if anyone would like tests (or can point me at some existing ones), I'm happy to oblige. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169730 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-09- Re-enable population count loop idiom recognization Shuxin Yang
- fix a bug which cause sigfault. - add two testing cases which was causing crash git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169687 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-08Revert the patches adding a popcount loop idiom recognition pass.Chandler Carruth
There are still bugs in this pass, as well as other issues that are being worked on, but the bugs are crashers that occur pretty easily in the wild. Test cases have been sent to the original commit's review thread. This reverts the commits: r169671: Fix a logic error. r169604: Move the popcnt tests to an X86 subdirectory. r168931: Initial commit adding the pass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169683 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-07s/AttrListPtr/AttributeSet/g to better label what this class is going to be ↵Bill Wendling
in the near future. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169651 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-07When we use the BLEND instruction that uses the MSB as a mask, we can removeNadav Rotem
the VSRI instruction before it since it does not affect the MSB. Thanks Craig Topper for suggesting this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169638 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-07X86: Prefer using VPSHUFD over VPERMIL because it has better throughput.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169624 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-06Replace r169459 with something safer. Rather than having computeMaskedBits toEvan Cheng
understand target implementation of any_extend / extload, just generate zero_extend in place of any_extend for liveouts when the target knows the zero_extend will be implicit (e.g. ARM ldrb / ldrh) or folded (e.g. x86 movz). rdar://12771555 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169536 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-06Remove unneeded function, since PR8156 was fixed over a year ago.Jakub Staszak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169534 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-06Simplify code.Jakub Staszak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169521 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-06Remove intrinsic specific instructions for (V)MOVQUmr with patterns pointing ↵Craig Topper
to the normal instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169482 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-06Mark MOVDQ(A/U)rm as ReMaterializable. Mark all MOVDQ(A/U) instructions as ↵Craig Topper
neverHasSideEffects. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169477 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-06Let targets provide hooks that compute known zero and ones for any_extendEvan Cheng
and extload's. If they are implemented as zero-extend, or implicitly zero-extend, then this can enable more demanded bits optimizations. e.g. define void @foo(i16* %ptr, i32 %a) nounwind { entry: %tmp1 = icmp ult i32 %a, 100 br i1 %tmp1, label %bb1, label %bb2 bb1: %tmp2 = load i16* %ptr, align 2 br label %bb2 bb2: %tmp3 = phi i16 [ 0, %entry ], [ %tmp2, %bb1 ] %cmp = icmp ult i16 %tmp3, 24 br i1 %cmp, label %bb3, label %exit bb3: call void @bar() nounwind br label %exit exit: ret void } This compiles to the followings before: push {lr} mov r2, #0 cmp r1, #99 bhi LBB0_2 @ BB#1: @ %bb1 ldrh r2, [r0] LBB0_2: @ %bb2 uxth r0, r2 cmp r0, #23 bhi LBB0_4 @ BB#3: @ %bb3 bl _bar LBB0_4: @ %exit pop {lr} bx lr The uxth is not needed since ldrh implicitly zero-extend the high bits. With this change it's eliminated. rdar://12771555 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169459 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-05Added a option to the disassembler to print immediates as hex.Kevin Enderby
This is for the lldb team so most of but not all of the values are to be printed as hex with this option. Some small values like the scale in an X86 address were requested to printed in decimal without the leading 0x. There may be some tweaks need to places that may still be in decimal that they want in hex. Specially for arm. I made my best guess. Any tweaks from here should be simple. I also did the best I know now with help from the C++ gurus creating the cleanest formatImm() utility function and containing the changes. But if someone has a better idea to make something cleaner I'm all ears and game for changing the implementation. rdar://8109283 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169393 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-05Simplified BLEND pattern matching for shuffles.Elena Demikhovsky
Generate VPBLENDD for AVX2 and VPBLENDW for v16i16 type on AVX2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169366 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-05Add x86 isel lowering logic to form bit test with inverted condition. e.g.Evan Cheng
x ^ -1. Patch by David Majnemer. rdar://12755626 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169339 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-04Removing an include of a deleted headerEli Bendersky
BUG=none Review URL: https://codereview.chromium.org/11280305
2012-12-04Revert the LOCALMODs implementing Nacl for the legacy JITEli Bendersky
BUG= http://code.google.com/p/nativeclient/issues/detail?id=3178 Review URL: https://codereview.chromium.org/11428121
2012-12-04Make NaCl naming consistent. The triple OSType is called NaCl and is representedEli Bendersky
textually as NativeClient. Also added a link to the native client project for readers unfamiliar with it. A Clang patch will follow shortly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169291 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-04Sort includes for all of the .h files under the 'lib' tree. These wereChandler Carruth
missed in the first pass because the script didn't yet handle include guards. Note that the script is now able to handle all of these headers without manual edits. =] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169224 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-03Use the new script to sort the includes of every file under lib.Chandler Carruth
Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-30Use isOSNaCl and minimize some LOCALMODsDavid Sehr
Another try after fumble-fingering git repos for https://codereview.chromium.org/11428097/ BUG= Review URL: https://codereview.chromium.org/11415231
2012-11-29Add isOSNaCl, and add Asm subclasses for NaClDavid Sehr
Removes some of the FIXME cruft that suggest we should use subclassing. BUG= Review URL: https://codereview.chromium.org/11316230
2012-11-29rdar://12100355 (part 1)Shuxin Yang
This revision attempts to recognize following population-count pattern: while(a) { c++; ... ; a &= a - 1; ... }, where <c> and <a>could be used multiple times in the loop body. TODO: On X8664 and ARM, __buildin_ctpop() are not expanded to a efficent instruction sequence, which need to be improved in the following commits. Reviewed by Nadav, really appreciate! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168931 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-29I changed hasAVX() to hasFp256() and hasAVX2() to hasInt256() in ↵Elena Demikhovsky
X86IselLowering.cpp. The logic was not changed, only names. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168875 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-28Remove all references to TargetInstrInfoImpl.Jakob Stoklund Olesen
This class has been merged into its super-class TargetInstrInfo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168760 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-27Merge commit '8d20b5f9ff609e70fae5c865931ab0f29e639d9c'Derek Schuff
Conflicts: lib/CodeGen/AsmPrinter/DwarfDebug.cpp lib/CodeGen/AsmPrinter/DwarfDebug.h lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp lib/Target/Mips/MipsISelDAGToDAG.cpp lib/Target/Mips/MipsInstrFPU.td lib/Target/Mips/MipsSubtarget.cpp lib/Target/Mips/MipsSubtarget.h lib/Target/X86/X86MCInstLower.cpp tools/Makefile tools/llc/llc.cpp
2012-11-27X86: do not fold load instructions such as [V]MOVS[S|D] to other instructionsManman Ren
when the destination register is wider than the memory load. These load instructions load from m32 or m64 and set the upper bits to zero, while the folded instructions may accept m128. rdar://12721174 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168710 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-26Remove the X86 Maximal Stack Alignment Check pass as it is no longer necessary.Chad Rosier
This pass was conservative in that it always reserved the FP to enable dynamic stack realignment, which allowed the RA to use aligned spills for vector registers. This happens even when spills were not necessary. The RA has since been improved to use unaligned spills when necessary. The new behavior is to realign the stack if the frame pointer was already reserved for some other reason, but don't reserve the frame pointer just because a function contains vector virtual registers. Part of rdar://12719844 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168627 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-26Normalize splat 256bit vectors with 8 elements.Jakub Staszak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168600 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-26Decouple MCInstBuilder from the streamer per Eli's request.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168597 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-26Add MCInstBuilder, a utility class to simplify MCInst creation similar to ↵Benjamin Kramer
MachineInstrBuilder. Simplify some repetitive code with it. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168587 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-21Fix execution domain for packed FMA4 instructions.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168417 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-21Mark ISD::FMA as Legal instead of custom for x86 with FMA3/FMA4. Needed so ↵Craig Topper
that llvm.muladd can be converted to ISD::FMA for fp_contract. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168413 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-21Make calcLiveInMask method static.Jakub Staszak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168409 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-21Make isScratchReg and isFPCopy methods static.Jakub Staszak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168407 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-20Add obvious constantness.Jakub Staszak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168396 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-20Intel OCL built-ins calling conventions now support MacOS 32-bit.Elena Demikhovsky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168359 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-16Add the Erlang/HiPE calling convention, patch by Yiannis Tsiouris.Duncan Sands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168166 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-16Use roundps/pd for llvm.ceil, llvm.trunc, llvm.rint, and llvm.nearbyint of ↵Craig Topper
vector types. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168141 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-15Return 0 instead of false.Jakub Staszak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168076 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-15Simplify code.Jakub Staszak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168064 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-15Merge commit '08e9cb46feb0c8e08e3d309a0f9fd75a04ca54fb'Derek Schuff
(svn r167699, also the 3.2 branch point) Conflicts: lib/Target/X86/X86Subtarget.cpp
2012-11-15Add llvm.ceil, llvm.trunc, llvm.rint, llvm.nearbyint intrinsics.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168025 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14Fix nacl.read.tp() intrinsic to not generate "addl %gs:0, %REG"Mark Seaborn
NaCl only allows using "mov" with a %gs prefix. The fix requires generating the mov instruction using a custom inserter that calls BuildMI(). Also convert the intrinsic's tests to use -filetype=asm rather than -filetype=obj. This avoids some limitations of llvm-objdump and is the more normal way to write LLVM tests. BUG=https://code.google.com/p/nativeclient/issues/detail?id=2837 TEST="llvm-lit test/NaCl" Review URL: https://codereview.chromium.org/11410058
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