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2012-12-26Mark VANDNPD/VANDNPDS as not commutable.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171085 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-26Remove alignment from a bunch more VEX encoded operations in the folding tables.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171082 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-26Remove alignment from folding table for VMOVUPD as an unaligned instruction ↵Craig Topper
it shouldn't require alignment... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171081 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-26Remove alignment requirements from (V)EXTRACTPS. This instruction does ↵Craig Topper
32-bit stores which aren't required to be aligned on SSE or AVX. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171080 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-26Remove alignment requirement from VCVTSS2SD in folding tables. Reverting ↵Craig Topper
r171049. This instruction doesn't require alignment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171078 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-25X86: Shave off one shuffle from the pcmpeqq sequence for SSE2 by making use ↵Benjamin Kramer
of and commutativity. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171064 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-25X86: Custom lower <2 x i64> eq and ne when SSE41 is not available.Benjamin Kramer
pcmpeqd, pshufd, pshufd, pand is cheaper than unpack + cmpq, sbbq, cmpq, sbbq + pack. Small speedup on loop-vectorized viterbi (-march=core2). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171063 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-25VCVTSS2SD requires a strict alignment. Thanks Elena.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171049 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-24Quiet gcc's -Wparenthesis warning. No functionality change.Nick Lewycky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171044 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-24Some x86 instructions can load/store one of the operands to memory. On SSE, ↵Nadav Rotem
this memory needs to be aligned. When these instructions are encoded in VEX (on AVX) there is no such requirement. This changes the folding tables and removes the alignment restrictions from VEX-encoded instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171024 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-23whitespaceNadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170997 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-23Rename a function.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170996 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-23Loop Vectorizer: Update the cost model of scatter/gather operations and makeNadav Rotem
them more expensive. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170995 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-22X86: Turn mul of <4 x i32> into pmuludq when no SSE4.1 is available.Benjamin Kramer
pmuludq is slow, but it turns out that all the unpacking and packing of the scalarized mul is even slower. 10% speedup on loop-vectorized paq8p. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170985 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-22X86: Emit vector sext as shuffle + sra if vpmovsx is not available.Benjamin Kramer
Also loosen the SSSE3 dependency a bit, expanded pshufb + psra is still better than scalarized loads. Fixes PR14590. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170984 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-21In some cases, due to scheduling constraints we copy the EFLAGS.Nadav Rotem
The only way to read the eflags is using push and pop. If we don't adjust the stack then we run over the first frame index. This is not something that we want to do, so we have to make sure that our machine function does not copy the flags. If it does then we have to emit the prolog that adjusts the stack. rdar://12896831 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170961 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-21X86: Match pmin/pmax as a target specific dag combine. This occurs during ↵Benjamin Kramer
vectorization. Part of PR14667. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170908 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-21X86: Match the SSE/AVX min/max vector ops using a custom node instead of ↵Benjamin Kramer
intrinsics This is very mechanical, no functionality change. Preparation for PR14667. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170898 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-21Add a missing "virtual" keyword.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170842 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-21Improve the X86 cost model for loads and stores.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170830 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20Add an MF argument to MI::copyImplicitOps().Jakob Stoklund Olesen
This function is often used to decorate dangling instructions, so a context reference is required to allocate memory for the operands. Also add a corresponding MachineInstrBuilder method. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170797 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20Remove MCTargetAsmLexer and its derived classes now that edis,Roman Divacky
its only user, is gone. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170699 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20Fix use-before-construction of X86TargetLowering.Richard Smith
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170654 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19MC: Add MCInstrDesc::mayAffectControlFlow() method.Jim Grosbach
MC disassembler clients (LLDB) are interested in querying if an instruction may affect control flow other than by virtue of being an explicit branch instruction. For example, instructions which write directly to the PC on some architectures. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170610 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19Remove the explicit MachineInstrBuilder(MI) constructor.Jakob Stoklund Olesen
Use the version that also takes an MF reference instead. It would technically be possible to extract an MF reference from the MI as MI->getParent()->getParent(), but that would not work for MIs that are not inserted into any basic block. Given the reasonably small number of places this constructor was used at all, I preferred the compile time check to a run time assertion. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170588 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19Remove edis - the enhanced disassembler. Fixes PR14654.Roman Divacky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170578 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19Transform (x&C)>V into (x&C)!=0 where possiblePaul Redmond
When the least bit of C is greater than V, (x&C) must be greater than V if it is not zero, so the comparison can be simplified. Although this was suggested in Target/X86/README.txt, it benefits any architecture with a directly testable form of AND. Patch by Kevin Schoedel git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170576 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19Change TargetLowering::getTypeForExtArgOrReturn to take and returnPatrik Hagglund
MVTs, instead of EVTs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170537 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19Change TargetLowering::RegisterTypeForVT to contain MVTs, instead ofPatrik Hagglund
EVTs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170535 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19Change TargetLowering::findRepresentativeClass to take an MVT, insteadPatrik Hagglund
of EVT. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170532 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19X86ISelLowering.cpp: Fix warnings. [-Wlogical-op-parentheses]NAKAMURA Takumi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170523 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19Optimized load + SIGN_EXTEND patterns in the X86 backend.Elena Demikhovsky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170506 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19Rename the 'Attributes' class to 'Attribute'. It's going to represent a ↵Bill Wendling
single attribute in the future. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170502 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-18Reverse order of checking SSE level when calculating compare cost, so we checkJakub Staszak
AVX2 before AVX. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170464 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17Remove EFLAGS from the BLSI/BLSMSK/BLSR patterns. The nodes created by DAG ↵Craig Topper
combine don't contain an EFLAGS def. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170308 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17Simplify BMI ANDN matching to use patterns instead of a DAG combine. Also ↵Craig Topper
add ANDN to isDefConvertible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170305 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17Add rest of BMI/BMI2 instructions to the folding tables as well as popcnt ↵Craig Topper
and lzcnt. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170304 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17Remove store forms of DEC/INC from isDefConvertible. Since they are stores ↵Craig Topper
they don't have a register def. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170303 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-15X86: Add a couple of target-specific dag combines that turn VSELECTS into ↵Benjamin Kramer
psubus if possible. We match the pattern "x >= y ? x-y : 0" into "subus x, y" and two special cases if y is a constant. DAGCombiner canonicalizes those so we first have to undo the canonicalization for those cases. The pattern occurs in gzip when the loop vectorizer is enabled. Part of PR14613. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170273 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-15Make '-mtune=x86_64' assume fast unaligned memory accesses.Chandler Carruth
Not all chips targeted by x86_64 have this feature, but a dramatically increasing number do. Specifying a chip-specific tuning parameter will continue to turn the feature on or off as appropriate for that particular chip, but the generic flag should try to achieve the best performance on the most widely available hardware. Today, the number of chips with fast UA access dwarfs those without in the x86-64 space. Note that this also brings LLVM's code generation for this '-march' flag more in line with that of modern GCCs. Reviewed by Dan Gohman. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170269 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-14FastIsel: Get PIC-style GV loads for NaCl64 even w/out 64-bit pointers.Jan Voung
Without this, the load would not be RIP relative, and will end up being relative to 0, which is R15. BUG= http://code.google.com/p/nativeclient/issues/detail?id=3219 TEST= ./scons bitcode=1 pnacl_generate_pexe=0 \ run_stack_frame_noopt_noframe_test \ run_unwind_trace_noopt_noframe_test \ run_stack_frame_noopt_frame_test \ run_unwind_trace_noopt_frame_test \ platform=x86-64 nacl_pic=1 Review URL: https://codereview.chromium.org/11575042
2012-12-14TypeLegalizer: Do not generate target specific nodes with illegal types, ↵Nadav Rotem
because we cant type-legalize them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170245 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-14Prevent FastISel X86_64 from generating bad instructions for NaCl.Jim Stichnoth
If the addressing mode matches certain patterns, then FastISel for the instruction is rejected and regular ISel is used, where X86DAGToDAGISel::LegalizeAddressingModeForNaCl() does the necessary transformations. The most common problem (which shows up in spec2k gcc and crafty) is when a register holds a negative offset indexing an interior pointer into a global struct/array, e.g. global_var[10+reg] where &global_var[10] is a precomputed constant and reg is negative. BUG= http://code.google.com/p/nativeclient/issues/detail?id=3211 TEST= On the x86-64 platform, run 176.gcc from spec2k with FastISel forced, e.g. by modifying pnacl-translate.py to set default FAST_TRANSLATION=1 and uncommenting the "-fast-isel" flag in the LLC_FLAGS_FAST_X8664 definition. Review URL: https://codereview.chromium.org/11543023
2012-12-13Fix a bogus commentEli Bendersky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170052 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-12Sorry about the churn. One more change to getOptimalMemOpType() hook. Did IEvan Cheng
mention the inline memcpy / memset expansion code is a mess? This patch split the ZeroOrLdSrc argument into two: IsMemset and ZeroMemset. The first indicates whether it is expanding a memset or a memcpy / memmove. The later is whether the memset is a memset of zero. It's totally possible (likely even) that targets may want to do different things for memcpy and memset of zero. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169959 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-12- Rename isLegalMemOpType to isSafeMemOpType. "Legal" is a very overloade term.Evan Cheng
Also added more comments to explain why it is generally ok to return true. - Rename getOptimalMemOpType argument IsZeroVal to ZeroOrLdSrc. It's meant to be true for loaded source (memcpy) or zero constants (memset). The poor name choice is probably some kind of legacy issue. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169954 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-12Avoid using lossy load / stores for memcpy / memset expansion. e.g.Evan Cheng
f64 load / store on non-SSE2 x86 targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169944 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11Revert EVT->MVT changes, r169836-169851, due to buildbot failures.Patrik Hagglund
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169854 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11Change TargetLowering::getTypeForExtArgOrReturn to take and returnPatrik Hagglund
MVTs, instead of EVTs. Accordingly, add bitsLT (and similar) to MVT. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169850 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-11Change TargetLowering::RegisterTypeForVT to contain MVTs, instead ofPatrik Hagglund
EVTs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169848 91177308-0d34-0410-b5e6-96231b3b80d8
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