| Age | Commit message (Expand) | Author |
|---|
| 2010-09-01 | Use movlps, movlpd, movss and movsd specific nodes instead of pattern matchin... | Bruno Cardoso Lopes |
| 2010-09-01 | minor change, simplify some logic | Bruno Cardoso Lopes |
| 2010-09-01 | Move some functions around so they can be used for some other to come function | Bruno Cardoso Lopes |
| 2010-08-31 | Use x86 specific MOVSLDUP node, add more patterns to match it and remove usel... | Bruno Cardoso Lopes |
| 2010-08-31 | Use x86 specific MOVSHDUP node and add more patterns to match it | Bruno Cardoso Lopes |
| 2010-08-31 | Use MOVHLPS node instead of matching using movhlps and movhlps_undef pattern ... | Bruno Cardoso Lopes |
| 2010-08-31 | Use MOVLHPS and MOVHLPS x86 nodes whenever possible. Also remove some useless... | Bruno Cardoso Lopes |
| 2010-08-31 | Use X86ISD::MOVSS and MOVSD to represent the movl mask pattern, also fix the ... | Bruno Cardoso Lopes |
| 2010-08-28 | fix the buildvector->insertp[sd] logic to not always create a redundant | Chris Lattner |
| 2010-08-28 | fix the BuildVector -> unpcklps logic to not do pointless shuffles | Chris Lattner |
| 2010-08-28 | improve comments in the unpcklps generating logic, introduce | Chris Lattner |
| 2010-08-28 | Clean up the logic of vector shuffles -> vector shifts. | Bruno Cardoso Lopes |
| 2010-08-27 | Properly handle passing of FP stuff to varargs function on Win64: | Anton Korobeynikov |
| 2010-08-26 | zap the now unused MVT::getIntVectorWithNumElements | Bruno Cardoso Lopes |
| 2010-08-26 | implement SplitVecOp_CONCAT_VECTORS, fixing the included testcase with SSE1. | Chris Lattner |
| 2010-08-26 | fix sse1 only codegen in x86-64 mode, which is something we | Chris Lattner |
| 2010-08-25 | Revert this for now, PUNPCKLDQ dont operate on v4f32 | Bruno Cardoso Lopes |
| 2010-08-25 | Fix nasty mingw32 bug, which e.g. prevented llvm-gcc bootstrap there. | Anton Korobeynikov |
| 2010-08-25 | PUNPCKLDQ should also be used for v4f32 | Bruno Cardoso Lopes |
| 2010-08-25 | teach lowering to get target specific nodes for pshufd, emulating the same is... | Bruno Cardoso Lopes |
| 2010-08-24 | Fix X86's isLegalAddressingMode to recognize that static addresses | Dan Gohman |
| 2010-08-24 | Use pshufhw and pshuflw in more cases and fix getTargetShuffleNode number of ... | Bruno Cardoso Lopes |
| 2010-08-23 | Start using target speficic nodes for shuffles: pshufhw and pshuflw | Bruno Cardoso Lopes |
| 2010-08-23 | Revert invalid r111792. Jump tables are not broken on x86-64 / coff, | Anton Korobeynikov |
| 2010-08-23 | Workaround broken jump tables on x86-64 COFF. | Michael J. Spencer |
| 2010-08-21 | Prepare LowerVECTOR_SHUFFLEv8i16 to use x86 target specific nodes directly | Bruno Cardoso Lopes |
| 2010-08-20 | This is the first step towards refactoring the x86 vector shuffle code. The | Bruno Cardoso Lopes |
| 2010-08-17 | More fixes for win64: | Anton Korobeynikov |
| 2010-08-14 | Rework how the non-sse2 memory barrier is lowered so that the | Eric Christopher |
| 2010-08-14 | improve indentation | Chris Lattner |
| 2010-08-13 | Fix comment to reflect code, and remove an unused argument | Bruno Cardoso Lopes |
| 2010-08-12 | Begin to support some vector operations for AVX 256-bit intructions. The long | Bruno Cardoso Lopes |
| 2010-08-11 | Use ISD::ADD instead of ISD::SUB with a negated constant. This | Dan Gohman |
| 2010-08-10 | Add AVX matching patterns to Packed Bit Test intrinsics. | Bruno Cardoso Lopes |
| 2010-08-10 | Support AVX 256-bit load and store intrinsics | Bruno Cardoso Lopes |
| 2010-08-05 | Support very basic (doesn't include ABI support in the front-end, varags, ...... | Bruno Cardoso Lopes |
| 2010-08-04 | Make x86-64 membarriers work without sse and clean up some of the | Eric Christopher |
| 2010-07-30 | Support all 128-bit AVX vector intrinsics. Most part of them I already | Bruno Cardoso Lopes |
| 2010-07-29 | Revert r109652, and remove the offending assert in loadRegFromStackSlot instead. | Jakob Stoklund Olesen |
| 2010-07-28 | Create a fixed stack object for varargs that is as large as any register. | Jakob Stoklund Olesen |
| 2010-07-28 | Implement a vectorized algorithm for <16 x i8> << <16 x i8> | Nate Begeman |
| 2010-07-27 | ~40% faster vector shl <4 x i32> on SSE 4.1 Larger improvements for smaller ... | Nate Begeman |
| 2010-07-26 | On x86, f32 / f64 nodes share the same registers as 128-bit vector values. | Evan Cheng |
| 2010-07-24 | Add an ILP scheduler. This is a register pressure aware scheduler that's | Evan Cheng |
| 2010-07-23 | The only supported calling convention for X86-64 uses | Dale Johannesen |
| 2010-07-22 | Custom lower the memory barrier instructions and add support | Eric Christopher |
| 2010-07-22 | 80-columns. | Eric Christopher |
| 2010-07-21 | Fix a couple issues with Win64 ABI | Nate Begeman |
| 2010-07-21 | Pulling out previous patch, must've run the tests in | Eric Christopher |
| 2010-07-21 | Lower MEMBARRIER on x86 and support processors without SSE2. | Eric Christopher |
