| Age | Commit message (Expand) | Author |
|---|
| 2004-11-15 | Update list of failing Benchmarks. | Brian Gaeke |
| 2004-11-15 | Expand Defs to encompass all the possibly-call-clobbered regs. | Brian Gaeke |
| 2004-11-14 | Fix problem with insertion point for ADJCALLSTACKDOWN. | Brian Gaeke |
| 2004-11-14 | Update lists of failing unit tests. | Brian Gaeke |
| 2004-11-14 | Fix NotTest - round up extraStack to the nearest doubleword, if it is | Brian Gaeke |
| 2004-11-14 | Update failing Benchmarks; point out that I'm skipping Shootout-C++. | Brian Gaeke |
| 2004-11-14 | Update expected UnitTests failures. | Brian Gaeke |
| 2004-11-14 | Rewrite outgoing arg handling to handle more weird corner cases. | Brian Gaeke |
| 2004-11-14 | Support UndefValue emission. | Brian Gaeke |
| 2004-11-04 | Handle "call" operands of type long/ulong passed in registers. | Brian Gaeke |
| 2004-10-29 | Change name of target lib to conform to new naming scheme. | Brian Gaeke |
| 2004-10-29 | Remove dependency on MRegisterInfo::getRegClass | Brian Gaeke |
| 2004-10-22 | Adjust rules for building .inc files due to Reid's changes of Makefile.rules | Misha Brukman |
| 2004-10-19 | * Add baseline structural JIT code, but disable the JIT to allow llvm-gcc builds | Misha Brukman |
| 2004-10-17 | Add support for unreachable and undef | Chris Lattner |
| 2004-10-14 | The field is called `imm22', not simply `imm' | Misha Brukman |
| 2004-10-14 | Synthetic instructions RET and RETL need to have all 3 parameters specified | Misha Brukman |
| 2004-10-14 | Class F2_1 already inherits the imm22 field from class F2 | Misha Brukman |
| 2004-10-14 | Generate the SparcV8 code emitter from .td files | Misha Brukman |
| 2004-10-14 | * In the F3_1 class, default asi to 0 because it's not currently used | Misha Brukman |
| 2004-10-14 | Add FSTOI, FDTOI (fp to integer cast) instructions. | Brian Gaeke |
| 2004-10-14 | Rewrite emitCastOperation, refactoring parts of it into emitIntegerCast, and | Brian Gaeke |
| 2004-10-14 | Add list of libc procedures we'll use, at some point. | Brian Gaeke |
| 2004-10-10 | Fix assertion failure when calling or returning from a function which | Brian Gaeke |
| 2004-10-10 | Implement eliminateCallFramePseudoInstr(). | Brian Gaeke |
| 2004-10-10 | Model calls as *both* using *and* killing O0..O5, because callees use the | Brian Gaeke |
| 2004-10-10 | Fix whitespace and wrap some long lines. | Brian Gaeke |
| 2004-10-09 | update according to tonight's info | Brian Gaeke |
| 2004-10-09 | Implement getModuleMatchQuality and getJITMatchQuality so that v8 will be the | Brian Gaeke |
| 2004-09-30 | I think this will handle double args. | Brian Gaeke |
| 2004-09-30 | Mark the instructions that have delay slots with the hasDelaySlot flag. | Brian Gaeke |
| 2004-09-30 | Use TargetMachine::hasDelaySlot() instead of our old switch statement | Brian Gaeke |
| 2004-09-29 | Update list of shootout programs that should be working. | Brian Gaeke |
| 2004-09-29 | Tell the target description that calls clobber registers O0...O5. | Brian Gaeke |
| 2004-09-29 | FITOD is spelled "fitod", not "fitos". Ouch. | Brian Gaeke |
| 2004-09-29 | Don't use .quad to output double constants. The assembler must have a bug or | Brian Gaeke |
| 2004-09-29 | Recognize FpMOVD as a move. | Brian Gaeke |
| 2004-09-29 | add results | Brian Gaeke |
| 2004-09-29 | Simplify copyConstantToRegister() for longs, using a pair of recursive calls. | Brian Gaeke |
| 2004-09-29 | Fix bug recognizing moves: isMoveInstr should only treat ORs with %g0 as | Brian Gaeke |
| 2004-09-29 | Use FpMOVD pseudo-instruction to move doubles around. | Brian Gaeke |
| 2004-09-29 | Add new FpMOVD pseudo-instruction, used to move doubles around. | Brian Gaeke |
| 2004-09-29 | Fix double and long alignment. | Brian Gaeke |
| 2004-09-29 | Put quotes around argument to .section directive. | Brian Gaeke |
| 2004-09-29 | Add createSparcV8FPMoverPass(). | Brian Gaeke |
| 2004-09-29 | Pass which converts FpMOVD (double move pseudoinstructions) to pairs | Brian Gaeke |
| 2004-09-27 | SparcV8 int regs are not only 32-bits in width, but they are 32-bit aligned! | Misha Brukman |
| 2004-09-26 | Fix the copy-pasto that Brian noticed: V8 int regs are 32-bits wide, not 64. | Misha Brukman |
| 2004-09-22 | Use the V8/V9 shared register file description | Misha Brukman |
| 2004-09-22 | Combine the F2 and F3 instruction classes into one file for simplicity | Misha Brukman |
