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path: root/lib/Target/PTX/PTXSubtarget.cpp
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2012-05-24Remove the PTX back-end and all of its artifacts (triple, etc.)Justin Holewinski
This back-end was deprecated in favor of the NVPTX back-end. NV_CONTRIB git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157417 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-18Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu
MSP430, PPC, PTX, Sparc, X86, XCore. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10Fix some leftover control reaches end of non-void function warnings.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147874 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-10Remove unnecessary default cases in switches that cover all enum values.David Blaikie
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147855 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20Unweaken vtables as per ↵David Blaikie
http://llvm.org/docs/CodingStandards.html#ll_virtual_anch git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146960 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24Move TargetRegistry and TargetSelect from Target to Support where they belong.Evan Cheng
These are strictly utilities for registering targets and components. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138450 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14Next round of MC refactoring. This patch factor MC table instantiations, MCEvan Cheng
registeration and creation code into XXXMCDesc libraries. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135184 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-11- Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfoEvan Cheng
and MCSubtargetInfo. - Added methods to update subtarget features (used when targets automatically detect subtarget features or switch modes). - Teach X86Subtarget to update MCSubtargetInfo features bits since the MCSubtargetInfo layer can be shared with other modules. - These fixes .code 16 / .code 32 support since mode switch is updated in MCSubtargetInfo so MC code emitter can do the right thing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134884 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-09Change createAsmParser to take a MCSubtargetInfo instead of triple,Evan Cheng
CPU, and feature string. Parsing some asm directives can change subtarget state (e.g. .code 16) and it must be reflected in other modules (e.g. MCCodeEmitter). That is, the MCSubtargetInfo instance must be shared. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134795 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08Eliminate asm parser's dependency on TargetMachine:Evan Cheng
- Each target asm parser now creates its own MCSubtatgetInfo (if needed). - Changed AssemblerPredicate to take subtarget features which tablegen uses to generate asm matcher subtarget feature queries. e.g. "ModeThumb,FeatureThumb2" is translated to "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134678 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07Compute feature bits at time of MCSubtargetInfo initialization.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134606 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01Rename XXXGenSubtarget.inc to XXXGenSubtargetInfo.inc for consistency.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134281 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01Rename TargetSubtarget to TargetSubtargetInfo for consistency.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134259 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01- Added MCSubtargetInfo to capture subtarget features and schedulingEvan Cheng
itineraries. - Refactor TargetSubtarget to be based on MCSubtargetInfo. - Change tablegen generated subtarget info to initialize MCSubtargetInfo and hide more details from targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134257 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-30Fix the ridiculous SubtargetFeatures API where it implicitly expects CPU name toEvan Cheng
be the first encoded as the first feature. It then uses the CPU name to look up features / scheduling itineray even though clients know full well the CPU name being used to query these properties. The fix is to just have the clients explictly pass the CPU name! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134127 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24PTX: Re-work target sm/compute selection and add some basic GPUJustin Holewinski
targets: g80, gt200, gf100(fermi) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133799 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-18PTX: add flag to disable mad/fma selectionJustin Holewinski
Patch by Dan Bailey git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131537 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-06PTX: add PTX 2.3 language targetJustin Holewinski
Patch by Wei-Ren Chen git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130980 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-20PTX: Add intrinsics to list of built-in intrinsics, which allows them to beJustin Holewinski
used by Clang. To help Clang integration, the PTX target has been split into two targets: ptx32 and ptx64, depending on the desired pointer size. - Add GCCBuiltin class to all intrinsics - Split PTX target into ptx32 and ptx64 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129851 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15PTX: Set PTX 2.0 as the minimum supported versionJustin Holewinski
- Remove PTX 1.4 code generation - Change type of intrinsics to .v4.i32 instead of .v4.i16 - Add and/or/xor integer instructions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127677 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-02Add 64-bit addressing to PTX backendChe-Liang Chiou
- Add '64bit' sub-target option. - Select 32-bit/64-bit loads/stores based on '64bit' option. - Fix function parameter order. Patch by Justin Holewinski git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126837 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-02Extend initial support for primitive types in PTX backendChe-Liang Chiou
- Allow i16, i32, i64, float, and double types, using the native .u16, .u32, .u64, .f32, and .f64 PTX types. - Allow loading/storing of all primitive types. - Allow primitive types to be passed as parameters. - Allow selection of PTX Version and Shader Model as sub-target attributes. - Merge integer/floating-point test cases for load/store. - Use .u32 instead of .s32 to conform to output from NVidia nvcc compiler. Patch by Justin Holewinski git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126824 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-18Add the exit instruction to the PTX target.Eric Christopher
Patch by Che-Liang Chiou <clchiou@gmail.com>! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114294 91177308-0d34-0410-b5e6-96231b3b80d8
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