Age | Commit message (Expand) | Author |
2013-03-22 | Hexagon: Add and enable memops setbit, clrbit, &,|,+,- for byte, short, and w... | Jyotsna Verma |
2013-02-22 | Remove code copied from GenRegisterInfo.inc. | Andrew Trick |
2013-02-21 | Move the eliminateCallFramePseudoInstr method from TargetRegisterInfo | Eli Bendersky |
2013-01-31 | [PEI] Pass the frame index operand number to the eliminateFrameIndex function. | Chad Rosier |
2013-01-02 | Move all of the header files which are involved in modelling the LLVM IR | Chandler Carruth |
2012-12-03 | Use the new script to sort the includes of every file under lib. | Chandler Carruth |
2012-09-04 | Porting Hexagon MI Scheduler to the new API. | Sergei Larin |
2012-05-30 | Fix some uses of getSubRegisters() to use getSubReg() instead. | Jakob Stoklund Olesen |
2012-05-10 | Hexagon V5 FP Support. | Sirish Pande |
2012-04-23 | Revert r155365, r155366, and r155367. All three of these have regression | Chandler Carruth |
2012-04-23 | Hexagon V5 (floating point) support. | Sirish Pande |
2012-04-18 | This reverts a long string of commits to the Hexagon backend. These | Chandler Carruth |
2012-04-16 | Hexagon V5 (Floating Point) Support. | Sirish Pande |
2012-03-17 | Reorder includes in Target backends to following coding standards. Remove som... | Craig Topper |
2012-03-04 | Use uint16_t to store registers in callee saved register tables to reduce siz... | Craig Topper |
2012-02-22 | Efficient pattern for store truncate. Patch by Evandro Menezes. | Sirish Pande |
2012-02-18 | Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430,... | Jia Liu |
2012-02-07 | Convert assert(0) to llvm_unreachable | Craig Topper |
2012-02-06 | Hexagon: Remove forbidden iostream includes (it introduces static initializers) | Benjamin Kramer |
2011-12-27 | Clean up some Release build warnings. | Benjamin Kramer |
2011-12-15 | Add MCTargetDesc library to Hexagon target | Tony Linthicum |
2011-12-12 | Hexagon backend support | Tony Linthicum |