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path: root/lib/Target/ARM/NEONPreAllocPass.cpp
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2010-09-13Convert some VTBL and VTBX instructions to use pseudo instructions prior toBob Wilson
register allocation. Remove the NEONPreAllocPass, which is no longer needed. Yeah!! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113818 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-13Switch all the NEON vld-lane and vst-lane instructions over to the newBob Wilson
pseudo-instruction approach. Change ARMExpandPseudoInsts to use a table to record all the NEON load/store information. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113812 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-03Finish converting the rest of the NEON VLD instructions to use pseudo-Bob Wilson
instructions prior to regalloc. Since it's getting a little close to the 2.8 branch deadline, I'll have to leave the rest of the instructions handled by the NEONPreAllocPass for now, but I didn't want to leave half of the VLD instructions converted and the other half not. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112983 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-02Convert VLD1 and VLD2 instructions to use pseudo-instructions untilBob Wilson
after regalloc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112825 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-28Use pseudo instructions for VST1 and VST2.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112357 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-26Use pseudo instructions for VST3.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112208 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-26Use pseudo instructions for VST1d64Q.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112170 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-26Revert svn 107892 (with changes to work with trunk). It caused a crash ifBob Wilson
a VLD result was not used (Radar 8355607). It should also fix pr7988, but I haven't verified that yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112118 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-25Start converting NEON load/stores to use pseudo instructions, beginning hereBob Wilson
with the VST4 instructions. Until after register allocation, we want to represent sets of adjacent registers by a single super-register. These VST4 pseudo instructions have a single QQ or QQQQ source register operand. They get expanded to the real VST4 instructions with 4 separate D register operands. Once this conversion is complete, we'll be able to remove the NEONPreAllocPass and avoid some fragile and hacky code elsewhere. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112108 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-06Reapply r110396, with fixes to appease the Linux buildbot gods.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110460 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-06Revert r110396 to fix buildbots.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110410 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-05Don't use PassInfo* as a type identifier for passes. Instead, use the ↵Owen Anderson
address of the static ID member as the sole unique type identifier. Clean up APIs related to this change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110396 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08The NEONPreAllocPass should never have to assign fixed registers anymore.Bob Wilson
This pass can go away entirely soon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107892 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08Convert EXTRACT_SUBREG to COPY when emitting machine instrs.Jakob Stoklund Olesen
EXTRACT_SUBREG no longer appears as a machine instruction. Use COPY instead. Add isCopy() checks in many places using isMoveInstr() and isExtractSubreg(). The isMoveInstr hook will be removed later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107879 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-16Don't attempt preserving conservative kill flags. We were doing it wrong.Jakob Stoklund Olesen
This is before LiveVariables anyway, where these kill flags are recalculated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106157 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-16Remove the hidden "neon-reg-sequence" option. The reg sequences are workingBob Wilson
now, so there's no need to disable them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106155 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-08Fix up a comment.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105591 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24Switch ARMRegisterInfo.td to use SubRegIndex and eliminate the parallel enumsJakob Stoklund Olesen
from ARMRegisterInfo.h git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104508 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-14Teach two-address pass to do some coalescing while eliminating REG_SEQUENCEEvan Cheng
instructions. e.g. %reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0 %reg1027<def> = EXTRACT_SUBREG %reg1026, 6 %reg1028<def> = EXTRACT_SUBREG %reg1026<kill>, 5 ... %reg1029<def> = REG_SEQUENCE %reg1028<kill>, 5, %reg1027<kill>, 6, %reg1028, 7, %reg1027, 8, %reg1028, 9, %reg1027, 10, %reg1030<kill>, 11, %reg1032<kill>, 12 After REG_SEQUENCE is eliminated, we are left with: %reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0 %reg1029:6<def> = EXTRACT_SUBREG %reg1026, 6 %reg1029:5<def> = EXTRACT_SUBREG %reg1026<kill>, 5 The regular coalescer will not be able to coalesce reg1026 and reg1029 because it doesn't know how to combine sub-register indices 5 and 6. Now 2-address pass will consult the target whether sub-registers 5 and 6 of reg1026 can be combined to into a larger sub-register (or combined to be reg1026 itself as is the case here). If it is possible, it will be able to replace references of reg1026 with reg1029 + the larger sub-register index. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103835 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-14Model VLD*_UPD and VLD*odd_UPD pair with REG_SEQUENCE.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103790 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-13Fix -Asserts warning.Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103694 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-12vst instructions are modeled as this:Evan Cheng
v1024 = REG_SEQUENCE ... v1025 = EXTRACT_SUBREG v1024, 5 v1026 = EXTRACR_SUBREG v1024, 6 = VSTxx <addr>, v1025, v1026 The REG_SEQUENCE ensures the sources that feed into the VST instruction are getting the right register allocation so they form a large super- register. The extract_subreg will be coalesced away all would just work: v1024 = REG_SEQUENCE ... = VSTxx <addr>, v1024:5, v1024:6 The problem is if the coalescer isn't run, the extract_subreg instructions would stick around and there is no assurance v1025 and v1026 will get the right registers. As a short term workaround, teach the NEON pre-allocation pass to transfer the sub-register indices over. An alternative would be do it 2addr pass when reg_sequence's are eliminated. But that *seems* wrong and require updating liveness information. Another alternative is to do this in the scheduler when the instructions are created. But that would mean somehow the scheduler this has to be done for correctness reason. That's yucky as well. So for now, we are leaving this in the target specific pass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103540 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-11Avoid breaking vstd when reg_sequence is not used.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103513 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-11Model some vst3 and vst4 with reg_sequence.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103453 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-10Model some vld3 instructions with REG_SEQUENCE.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103437 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-10Model vld2 / vst2 with reg_sequence.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103411 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that itDan Gohman
doesn't have to guess. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103194 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-05Do not pre-allocate references of D registers pairs if they are extracted ↵Evan Cheng
from the same Q register and are in the right order. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103124 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-04Do not pre-allocate for registers which form a REG_SEQUENCE.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103041 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-23Change VST1 instructions for loading Q register values to operate on pairsBob Wilson
of D registers. Add a separate VST1q instruction with a Q register source operand for use by storeRegToStackSlot. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99265 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-23Change VLD1 instructions for loading Q register values to operate on pairsBob Wilson
of D registers. Add a separate VLD1q instruction with a Q register destination operand for use by loadRegFromStackSlot. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99261 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-22Rename some VLD1/VST1 instructions to match the implementation, i.e., theBob Wilson
corresponding NEON instructions, instead of operation they are currently used for. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99189 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-20Re-commit r98683 ("remove redundant writeback flag from ARM address mode 6")Bob Wilson
with changes to add a separate optional register update argument. Change all the NEON instructions with address register writeback to use it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99095 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-20Rename some instructions for consistency and sanity: use "_UPD" suffix forBob Wilson
load/stores with address register writeback, and use "odd" suffix to distinguish instructions to access odd numbered registers (instead of "a" and "b"). No functional changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99066 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-16Revert 98683. It is breaking something in the disassembler.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98692 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-16Remove redundant writeback flag from ARM address mode 6. Also remove theBob Wilson
optional register update argument, which is currently unused -- when we add support for that, it can just be a separate operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98683 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-03improve portability to avoid conflicting with std::next in c++'0x.Chris Lattner
Patch by Howard Hinnant! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90365 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-07Support alignment specifier for NEON vld/vst instructionsJim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86404 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-25Remove VISIBILITY_HIDDEN from class/struct found inside anonymous namespaces.Nick Lewycky
Chris claims we should never have visibility_hidden inside any .cpp file but that's still not true even after this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85042 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-09Add codegen support for NEON vst4lane intrinsics with 128-bit vectors.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83600 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-08Add codegen support for NEON vst3lane intrinsics with 128-bit vectors.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83598 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-08Add codegen support for NEON vst2lane intrinsics with 128-bit vectors.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83596 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-08Add codegen support for NEON vld4lane intrinsics with 128-bit vectors.Bob Wilson
Also fix some copy-and-paste errors in previous changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83590 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-08Add codegen support for NEON vld3lane intrinsics with 128-bit vectors.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83585 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-08Add codegen support for NEON vld2lane intrinsics with 128-bit vectors.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83568 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-08Add codegen support for NEON vst4 intrinsics with <1 x i64> vectors.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83526 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-08Add codegen support for NEON vst3 intrinsics with <1 x i64> vectors.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83518 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-08Add codegen support for NEON vst2 intrinsics with <1 x i64> vectors.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83513 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-07Add codegen support for NEON vld4 intrinsics with <1 x i64> vectors.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83508 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-07Add codegen support for NEON vld3 intrinsics with <1 x i64> vectors.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83506 91177308-0d34-0410-b5e6-96231b3b80d8
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