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path: root/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp
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2010-10-01Rename the AsmPrinter directory to InstPrinter for those targets that haveJim Grosbach
been MC-ized for assembly printing. MSP430 is mostly so, but still has the asm printer and lowering code in the printer subdir for the moment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115360 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30Now that the pseudos that needed this are all custom lowered, we can go backJim Grosbach
to an empty PrintSpecial() git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115128 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30Nuke it from orbit. It's the only way to be sure.Jim Grosbach
(Kill the dead non-MC asm printer for the ARM target.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115127 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22Add PrintSpecial() handling for in ARM MC instruction printer.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114563 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-18PC-relative pseudo instructions are lowered and printed directly. Any encounterJim Grosbach
with one in the generic printing code is an error. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114242 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17Teach the (non-MC) instruction printer to use the cannonical names for push/pop,Jim Grosbach
and shift instructions on ARM. Update the tests to match. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114230 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17Hook up verbose asm comment printing for SOImm operands in MC printerJim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114215 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-16MC-ization of the PICLDR pseudo. Next up, adding the other variantsJim Grosbach
(PICLDRB, et. al.) and PICSTR* git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114098 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-16Remove support for "dregpair" operand modifier, now that it is no longer beingBob Wilson
used for anything. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114067 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-16store MC FP immediates as a double instead of as an APFloat, thus avoiding anJim Grosbach
unnecessary dtor for MCOperand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114064 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15Add support for the 'lane' modifier on vdup operandsJim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114030 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15Reduce dependencies in the ARM MC instruction printer.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114009 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15Add support for floating point immediates to MC instruction printing. ARMJim Grosbach
VFP instructions use it for loading some constants, so implement that handling. Not thrilled with adding a member to MCOperand, but not sure there's much of a better option that's not pretty fragile (like putting a double in the union instead and just assuming that's good enough). Suggestions welcome... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113996 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-14Reapply r113875 with additional cleanups.Jim Grosbach
"The register specified for a dregpair is the corresponding Q register, so to get the pair, we need to look up the sub-regs based on the qreg. Create a lookup function since we don't have access to TargetRegisterInfo here to be able to use getSubReg(ARM::dsub_[01])." Additionaly, fix the NEON VLD1* and VST1* instruction patterns not to use the dregpair modifier for the 2xdreg versions. Explicitly specifying the two registers as operands is more correct and more consistent with the other instruction patterns. This enables further cleanup of special case code in the disassembler as a nice side-effect. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113903 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-14revert 113875 momentarilly. Need to fix the MC disassembler to handle theJim Grosbach
change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113878 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-14trailing whitespace cleanupJim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113877 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-14The register specified for a dregpair is the corresponding Q register, so toJim Grosbach
get the pair, we need to look up the sub-regs based on the qreg. Create a lookup function since we don't have access to TargetRegisterInfo here to be able to use getSubReg(ARM::dsub_[01]). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113875 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-27Change ARM VFP VLDM/VSTM instructions to use addressing mode #4, just likeBob Wilson
all the other LDM/STM instructions. This fixes asm printer crashes when compiling with -O0. I've changed one of the NEON tests (vst3.ll) to run with -O0 to check this in the future. Prior to this change VLDM/VSTM used addressing mode #5, but not really. The offset field was used to hold a count of the number of registers being loaded or stored, and the AM5 opcode field was expanded to specify the IA or DB mode, instead of the standard ADD/SUB specifier. Much of the backend was not aware of these special cases. The crashes occured when rewriting a frameindex caused the AM5 offset field to be changed so that it did not have a valid submode. I don't know exactly what changed to expose this now. Maybe we've never done much with -O0 and NEON. Regardless, there's no longer any reason to keep a count of the VLDM/VSTM registers, so we can use addressing mode #4 and clean things up in a lot of places. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112322 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-16Rename sat_shift operand to shift_imm, in preparation for using it for otherBob Wilson
instructions besides saturate instructions. No functional changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111168 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-12Cleaned up the for-disassembly-only entries in the arm instruction table so thatJohnny Chen
the memory barrier variants (other than 'SY' full system domain read and write) are treated as one instruction with option operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110951 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11Move the ARM SSAT and USAT optional shift amount operand out of theBob Wilson
instruction opcode. This also fixes part of PR7792. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110875 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-05ARM "rrx" shift operands do not have an immediate. PR7790.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110292 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-14Remove restriction on NEON alignment values. Some of the NEON ld/stBob Wilson
instructions use different values (e.g., 2-byte or 4-byte alignment). Also fix ARMInstPrinter to print these alignments as bits instead of bytes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108386 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-13Move NEON "modified immediate" encode/decode into ARMAddressingModes.h toBob Wilson
avoid replicated code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108227 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-02Fix incorrect asm-printing of some NEON immediates. Fix weak testcase soBob Wilson
that it checks the immediate values, not just the instructions opcodes. Radar 8110263. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107487 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-11Add instruction encoding for the Neon VMOV immediate instruction. This changesBob Wilson
the machine instruction representation of the immediate value to be encoded into an integer with similar fields as the actual VMOV instruction. This makes things easier for the disassembler, since it can just stuff the bits into the immediate operand, but harder for the asm printer since it has to decode the value to be printed. Testcase for the encoding will follow later when MC has more support for ARM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105836 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24Switch ARMRegisterInfo.td to use SubRegIndex and eliminate the parallel enumsJakob Stoklund Olesen
from ARMRegisterInfo.h git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104508 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-12Add support for movi32 of global values to the new (MC) asm printer.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103576 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-16Fixed a bug in DisassembleN1RegModImmFrm() where a break stmt was missing for aJohnny Chen
case. Also, the 0xFF hex literal involved in the shift for ESize64 should be suffixed "ul" to preserve the shift result. Implemented printHex*ImmOperand() by copying from ARMAsmPrinter.cpp and added a test case for DisassembleN1RegModImmFrm()/printHex64ImmOperand(). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101557 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-16In the same spirit of r101524, which removed the assert() from ↵Johnny Chen
printAddrMode2OffsetOperand(), this patch removes the assert() from printAddrMode3OffsetOperand() and adds a test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101529 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-16Remove the assert() from printAddrMode2OffsetOperand(). "#0 and #-0" areJohnny Chen
considered legal instructions. Refs: A8.6.51 LDC, LDC2 (immediate) -- page A8-107, A8.6.58 LDR (immediate, ARM) -- page A8-121, and A8.6.194 STR (immediate, ARM) -- page A8-395. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101524 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-13Replace r101053 with a fix for getSOImmValRotate() so that it will correctlyBob Wilson
recognize all the valid rotated immediates. This fixes the disassembler issue and will also help codegen for some unusual constant values. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101114 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-12Fixed a crasher in arm disassembler within ARMInstPrinter.cpp after callingJohnny Chen
ARM_AM::getSoImmVal(V) with a legitimate so_imm value: #245 rotate right by 2. Introduce ARM_AM::getSOImmValOneOrNoRotate(unsigned Arg) which is called from ARMInstPrinter.cpp's printSOImm() function, replacing ARM_AM::getSOImmVal(V). [12:44:43] johnny:/Volumes/data/llvm/git/trunk (local-trunk) $ gdb Debug/bin/llvm-mc GNU gdb 6.3.50-20050815 (Apple version gdb-1346) (Fri Sep 18 20:40:51 UTC 2009) Copyright 2004 Free Software Foundation, Inc. GDB is free software, covered by the GNU General Public License, and you are welcome to change it and/or distribute copies of it under certain conditions. Type "show copying" to see the conditions. There is absolutely no warranty for GDB. Type "show warranty" for details. This GDB was configured as "x86_64-apple-darwin"...Reading symbols for shared libraries ... done (gdb) set args -triple=arm-apple-darwin9 -debug-only=arm-disassembler --disassemble (gdb) r Starting program: /Volumes/data/llvm/git/trunk/Debug/bin/llvm-mc -triple=arm-apple-darwin9 -debug-only=arm-disassembler --disassemble Reading symbols for shared libraries ++. done 0xf5 0x71 0xf0 0x53 Opcode=201 Name=MVNi Format=ARM_FORMAT_DPFRM(4) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ------------------------------------------------------------------------------------------------- | 0: 1: 0: 1| 0: 0: 1: 1| 1: 1: 1: 1| 0: 0: 0: 0| 0: 1: 1: 1| 0: 0: 0: 1| 1: 1: 1: 1| 0: 1: 0: 1| ------------------------------------------------------------------------------------------------- mvnpls r7, Assertion failed: (V != -1 && "Not a valid so_imm value!"), function printSOImm, file ARMInstPrinter.cpp, line 229. Program received signal SIGABRT, Aborted. 0x00007fff88c65886 in __kill () (gdb) bt #0 0x00007fff88c65886 in __kill () #1 0x00007fff88d05eae in abort () #2 0x00007fff88cf2ef0 in __assert_rtn () #3 0x000000010020e422 in printSOImm (O=@0x1010bdf80, V=-1, VerboseAsm=false, MAI=0x1020106d0) at ARMInstPrinter.cpp:229 #4 0x000000010020e5fe in llvm::ARMInstPrinter::printSOImmOperand (this=0x1020107e0, MI=0x7fff5fbfee70, OpNum=1, O=@0x1010bdf80) at ARMInstPrinter.cpp:254 #5 0x00000001001ffbc0 in llvm::ARMInstPrinter::printInstruction (this=0x1020107e0, MI=0x7fff5fbfee70, O=@0x1010bdf80) at ARMGenAsmWriter.inc:3236 #6 0x000000010020c27c in llvm::ARMInstPrinter::printInst (this=0x1020107e0, MI=0x7fff5fbfee70, O=@0x1010bdf80) at ARMInstPrinter.cpp:182 #7 0x000000010003cbff in PrintInsts (DisAsm=@0x10200f4e0, Printer=@0x1020107e0, Bytes=@0x7fff5fbff060, SM=@0x7fff5fbff078) at Disassembler.cpp:65 #8 0x000000010003c8b4 in llvm::Disassembler::disassemble (T=@0x1010c13c0, Triple=@0x1010b6798, Buffer=@0x102010690) at Disassembler.cpp:153 #9 0x000000010004095c in DisassembleInput (ProgName=0x7fff5fbff3f0 "/Volumes/data/llvm/git/trunk/Debug/bin/llvm-mc") at llvm-mc.cpp:347 #10 0x000000010003eefb in main (argc=4, argv=0x7fff5fbff298) at llvm-mc.cpp:374 (gdb) q The program is running. Exit anyway? (y or n) y [13:36:26] johnny:/Volumes/data/llvm/git/trunk (local-trunk) $ git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101053 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-04fix an ugly wart in the MCInstPrinter api where theChris Lattner
raw_ostream to print an instruction to had to be specified at MCInstPrinter construction time instead of being able to pick at each call to printInstruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100307 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-04change a ton of code to not implicitly use the "O" raw_ostreamChris Lattner
member of AsmPrinter. Instead, pass it in explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100306 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-20Re-commit r98683 ("remove redundant writeback flag from ARM address mode 6")Bob Wilson
with changes to add a separate optional register update argument. Change all the NEON instructions with address register writeback to use it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99095 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-19Fix -Asserts warnings.Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98928 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-17Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrmJohnny Chen
instructions to help disassembly. We also changed the output of the addressing modes to omit the '+' from the assembler syntax #+/-<imm> or +/-<Rm>. See, for example, A8.6.57/58/60. And modified test cases to not expect '+' in +reg or #+num. For example, ; CHECK: ldr.w r9, [r7, #28] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98745 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-16Revert 98683. It is breaking something in the disassembler.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98692 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-16Remove redundant writeback flag from ARM address mode 6. Also remove theBob Wilson
optional register update argument, which is currently unused -- when we add support for that, it can just be a separate operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98683 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-16Remove redundant writeback flag in ARM addressing mode 5.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98648 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-16Remove the writeback flag from ARM's address mode 4. Now that we have separateBob Wilson
instructions for ld/st with writeback, the flag is completely redundant. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98643 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-16Fix unused variable warnings.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98642 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-16--- Reverse-merging r98637 into '.':Bob Wilson
U test/CodeGen/ARM/tls2.ll U test/CodeGen/ARM/arm-negative-stride.ll U test/CodeGen/ARM/2009-10-30.ll U test/CodeGen/ARM/globals.ll U test/CodeGen/ARM/str_pre-2.ll U test/CodeGen/ARM/ldrd.ll U test/CodeGen/ARM/2009-10-27-double-align.ll U test/CodeGen/Thumb2/thumb2-strb.ll U test/CodeGen/Thumb2/ldr-str-imm12.ll U test/CodeGen/Thumb2/thumb2-strh.ll U test/CodeGen/Thumb2/thumb2-ldr.ll U test/CodeGen/Thumb2/thumb2-str_pre.ll U test/CodeGen/Thumb2/thumb2-str.ll U test/CodeGen/Thumb2/thumb2-ldrh.ll U utils/TableGen/TableGen.cpp U utils/TableGen/DisassemblerEmitter.cpp D utils/TableGen/RISCDisassemblerEmitter.h D utils/TableGen/RISCDisassemblerEmitter.cpp U Makefile.rules U lib/Target/ARM/ARMInstrNEON.td U lib/Target/ARM/Makefile U lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp U lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp U lib/Target/ARM/AsmPrinter/ARMInstPrinter.h D lib/Target/ARM/Disassembler U lib/Target/ARM/ARMInstrFormats.td U lib/Target/ARM/ARMAddressingModes.h U lib/Target/ARM/Thumb2ITBlockPass.cpp git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98640 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-16Initial ARM/Thumb disassembler check-in. It consists of a tablgen backendJohnny Chen
(RISCDisassemblerEmitter) which emits the decoder functions for ARM and Thumb, and the disassembler core which invokes the decoder function and builds up the MCInst based on the decoded Opcode. Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrm instructions to help disassembly. We also changed the output of the addressing modes to omit the '+' from the assembler syntax #+/-<imm> or +/-<Rm>. See, for example, A8.6.57/58/60. And modified test cases to not expect '+' in +reg or #+num. For example, ; CHECK: ldr.w r9, [r7, #28] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98637 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-16Stop using the old pre-UAL syntax for LDM/STM instruction suffixes.Bob Wilson
This does not move entirely to UAL syntax, since the default "increment after" suffix is empty but we still use "IA" for that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98635 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-02AL is an optional mnemonic extension for always, except in IT instructions.Johnny Chen
Add printMandatoryPredicateOperand() PrintMethod for IT predicate printing. Ref: A8.3 Conditional execution git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97571 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-03sink handling of target-independent machine instrs (otherChris Lattner
than DEBUG_VALUE :( ) into the target indep AsmPrinter.cpp file. This allows elimination of the NO_ASM_WRITER_BOILERPLATE hack among other things. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95177 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-25Implemented ARMInstPrinter::printThumbS4ImmOperand().Johnny Chen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94457 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-18remove the MAI argument to MCExpr::print and switch overthing to use << when ↵Chris Lattner
printing them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93699 91177308-0d34-0410-b5e6-96231b3b80d8
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