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2012-03-17Reorder includes to match coding standards. Fix an issue or two exposed by that.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152978 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-18Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu
MSP430, PPC, PTX, Sparc, X86, XCore. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20Unweaken vtables as per ↵David Blaikie
http://llvm.org/docs/CodingStandards.html#ll_virtual_anch git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146960 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24Switch ARMRegisterInfo.td to use SubRegIndex and eliminate the parallel enumsJakob Stoklund Olesen
from ARMRegisterInfo.h git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104508 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-14Teach two-address pass to do some coalescing while eliminating REG_SEQUENCEEvan Cheng
instructions. e.g. %reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0 %reg1027<def> = EXTRACT_SUBREG %reg1026, 6 %reg1028<def> = EXTRACT_SUBREG %reg1026<kill>, 5 ... %reg1029<def> = REG_SEQUENCE %reg1028<kill>, 5, %reg1027<kill>, 6, %reg1028, 7, %reg1027, 8, %reg1028, 9, %reg1027, 10, %reg1030<kill>, 11, %reg1032<kill>, 12 After REG_SEQUENCE is eliminated, we are left with: %reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0 %reg1029:6<def> = EXTRACT_SUBREG %reg1026, 6 %reg1029:5<def> = EXTRACT_SUBREG %reg1026<kill>, 5 The regular coalescer will not be able to coalesce reg1026 and reg1029 because it doesn't know how to combine sub-register indices 5 and 6. Now 2-address pass will consult the target whether sub-registers 5 and 6 of reg1026 can be combined to into a larger sub-register (or combined to be reg1026 itself as is the case here). If it is possible, it will be able to replace references of reg1026 with reg1029 + the larger sub-register index. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103835 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-14Added a QQQQ register file to model 4-consecutive Q registers.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103760 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06Re-apply 103156 and 103157. 103156 didn't break anything. 10315 exposed a ↵Evan Cheng
coalescer bug that's fixed by 103170. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103172 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06Revert r103156 since it was breaking the build bots.Eric Christopher
Reverse-merging r103156 into '.': U lib/Target/ARM/ARMInstrNEON.td U lib/Target/ARM/ARMRegisterInfo.h U lib/Target/ARM/ARMBaseRegisterInfo.cpp U lib/Target/ARM/ARMBaseInstrInfo.cpp U lib/Target/ARM/ARMRegisterInfo.td git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103159 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06Adding pseudo 256-bit registers QQ0 . . . QQ7 to represent pairs of Q ↵Evan Cheng
registers. These will be used to model VLD2 / VST2 instructions in order to get substantially better codegen for them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103156 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-06Add codegen support for NEON vld2 operations on quad registers.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83422 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-08Push methods into base class in preparation for sharing.David Goodwin
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75020 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-08Start breaking out common base functionality for register info.David Goodwin
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75016 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27Simplify a bitAnton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74385 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-27ARM refactoring. Step 2: split RegisterInfoAnton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74384 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-18- Update register allocation hint after coalescing. This is done by the ↵Evan Cheng
target since the hint is target dependent. This is important for ARM register pair hints. - Register allocator should resolve the second part of the hint (register number) before passing it to the target since it knows virtual register to physical register mapping. - More fixes to get ARM load / store double word working. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73671 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-15Part 1.Evan Cheng
- Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent. - Allow targets to specify alternative register allocation orders based on allocation hint. Part 2. - Use the register allocation hint system to implement more aggressive load / store multiple formation. - Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g. v1025 = LDR v1024, 0 v1026 = LDR v1024, 0 => v1025,v1026 = LDRD v1024, 0 If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair. - Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions. This is work in progress, not yet enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73381 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-07PR2985 / <rdar://problem/6584986>Jim Grosbach
When compiling in Thumb mode, only the low (R0-R7) registers are available for most instructions. Breaking the low registers into a new register class handles this. Uses of R12, SP, etc, are handled explicitly where needed with copies inserted to move results into low registers where the rest of the code generator can deal with them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68545 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-13Remove refs to non-DebugLoc versions of BuildMI from ARM.Dale Johannesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64429 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-06Move getPointerRegClass from TargetInstrInfo to TargetRegisterInfo.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63938 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-12Fix encoding of single-precision VFP registers.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59102 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-31Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48995 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-10Rename MRegisterInfo to TargetRegisterInfo.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46930 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-07Move even more functionality from MRegisterInfo into TargetInstrInfo.Owen Anderson
Some day I'll get it all moved over... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45672 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-04Move some more functionality from MRegisterInfo to TargetInstrInfo.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45603 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-01Move some more instruction creation methods from RegisterInfo into InstrInfo.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45484 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-29Remove attribution from file headers, per discussion on llvmdev.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-05Add a argument to storeRegToStackSlot and storeRegToAddr to specify whetherEvan Cheng
the stored register is killed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44600 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-02Remove redundant foldMemoryOperand variants and other code clean up.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44517 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-01Allow some reloads to be folded in multi-use cases. Specifically testl r, r ↵Evan Cheng
-> cmpl [mem], 0. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44479 91177308-0d34-0410-b5e6-96231b3b80d8
2007-11-13Add parameter to getDwarfRegNum to permit targetsDale Johannesen
to use different mappings for EH and debug info; no functional change yet. Fix warning in X86CodeEmitter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44056 91177308-0d34-0410-b5e6-96231b3b80d8
2007-11-11Use TableGen to emit information for dwarf register numbers. Anton Korobeynikov
This makes DwarfRegNum to accept list of numbers instead. Added three different "flavours", but only slightly tested on x86-32/linux. Please check another subtargets if possible, git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43997 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-18- Added getOpcodeAfterMemoryUnfold(). It doesn't unfold an instruction, but ↵Evan Cheng
only returns the opcode of the instruction post unfolding. - Fix some copy+paste bugs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43153 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-18Use SmallVectorImpl instead of SmallVector with hardcoded size in MRegister ↵Evan Cheng
public interface. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43150 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-05- Added a few target hooks to generate load / store instructions from / to anyEvan Cheng
address (not just from / to frameindexes). - Added target hooks to unfold load / store instructions / SDNodes into separate load, data processing, store instructions / SDNodes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42621 91177308-0d34-0410-b5e6-96231b3b80d8
2007-09-26Allow copyRegToReg to emit cross register classes copies.Evan Cheng
Tested with "make check"! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42346 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-30Add a variant of foldMemoryOperand to fold any load / store, not just load / ↵Evan Cheng
store from / to stack slots. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41597 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-19Change instruction description to split OperandList into OutOperandList andEvan Cheng
InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-14Long live the exception handling!Anton Korobeynikov
This patch fills the last necessary bits to enable exceptions handling in LLVM. Currently only on x86-32/linux. In fact, this patch adds necessary intrinsics (and their lowering) which represent really weird target-specific gcc builtins used inside unwinder. After corresponding llvm-gcc patch will land (easy) exceptions should be more or less workable. However, exceptions handling support should not be thought as 'finished': I expect many small and not so small glitches everywhere. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39855 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-01eliminateFrameIndex() change.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36626 91177308-0d34-0410-b5e6-96231b3b80d8
2007-05-01Under normal circumstances, when a frame pointer is not required, we reserveEvan Cheng
argument space for call sites in the function immediately on entry to the current function. This eliminates the need for add/sub sp brackets around call sites. However, this is not always a good idea. If the "call frame" is large and the target load / store instructions have small immediate field to encode sp offset, this can cause poor codegen. In the worst case, this can make it impossible to scavenge a register if the reserved spill slot is pushed too far apart from sp / fp. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36607 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-20Added MRegisterInfo hook to re-materialize an instruction.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35205 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-06Scavenge a register using the register scavenger when needed.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34966 91177308-0d34-0410-b5e6-96231b3b80d8
2007-02-28Make requiresRegisterScavenging determination on a per MachineFunction basis.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34711 91177308-0d34-0410-b5e6-96231b3b80d8
2007-02-28PEI now passes a RegScavenger ptr to eliminateFrameIndex.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34707 91177308-0d34-0410-b5e6-96231b3b80d8
2007-02-27Let MRegisterInfo now owns RegScavenger; eliminateFrameIndex must preserve ↵Evan Cheng
register kill info. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34692 91177308-0d34-0410-b5e6-96231b3b80d8
2007-02-23Add option to turn on register scavenger; By default, spills kills the ↵Evan Cheng
register being stored. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34514 91177308-0d34-0410-b5e6-96231b3b80d8
2007-02-21Support to provide exception and selector registers.Jim Laskey
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34482 91177308-0d34-0410-b5e6-96231b3b80d8
2007-02-19Re-apply my liveintervalanalysis changes. Now with PR1207 fixes.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34428 91177308-0d34-0410-b5e6-96231b3b80d8
2007-02-19For PR1207:Reid Spencer
Revert patches that caused the problem. Evan, please investigate and reapply when you've discovered the problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34399 91177308-0d34-0410-b5e6-96231b3b80d8
2007-02-17Added getReservedRegs().Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34376 91177308-0d34-0410-b5e6-96231b3b80d8
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