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just issues an error for the moment. The front end won't yet generate these
intrinsics for ARM, so this is behind the scenes until complete.
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progress.
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atomic operations intrinsics.
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- Also support the 'q' NEON registers asm code.
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both source operands. In the canonical form, the 2nd operand is changed to an
undef and the shuffle mask is adjusted to only reference elements from the 1st
operand. Radar 7434842.
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than doing the same via constpool:
1. Load from constpool costs 3 cycles on A9, movt/movw pair - just 2.
2. Load from constpool might stall up to 300 cycles due to cache miss.
3. Movt/movw does not use load/store unit.
4. Less constpool entries => better compiler performance.
This is only enabled on ELF systems, since darwin does not have needed
relocations (yet).
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Note that "hasDotLocAndDotFile"-style debug info was already broken;
people wanting this functionality should implement it in the
AsmPrinter/DwarfWriter code.
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slots. The AsmPrinter will use this information to determine whether to
print a spill/reload comment.
Remove default argument values. It's too easy to pass a wrong argument
value when multiple arguments have default values. Make everything
explicit to trap bugs early.
Update all targets to adhere to the new interfaces..
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folded into target icmp instructions.
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ARMFunctionInfo::createConstPoolEntryUId() instead.
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constant pool so they don't get wrapped separately.
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is unconditional. Making it still use the libcall when optimizing for size
would be a good adjustment.
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enable more machine licm. More changes coming.
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void f (int a1, int a2, int a3, int a4, int a5,...)
In ARMTargetLowering::LowerFormalArguments if the function has 4 or
more regular arguments we used to set VarArgsFrameIndex using an
offset of 0, which is only correct if the function has exactly 4
regular arguments.
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clang/test/CodeGen/indirect-goto.c runs! (unoptimized)
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I can see with the original code was that I forgot that this runs after
type legalization and hence the result type will always be i32. (Custom
legalization of EXTRACT_VECTOR_ELT is only enabled for vector types with
8- and 16-bit elements.)
Regarding the FIXME comment: any information about sign and zero-extension
should be captured by separate extension operations. The DAG combiner should
handle those to produce either VGETLANEu or VGETLANEs, and that seems to be
working now. If there are cases that we're missing, let me know.
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by creating TargetConstants during instruction selection instead of during
legalization.
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multiple instructions, the expansion is done during selection so there is
no need to do anything special during legalization.
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something similar)
and register spills.
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This fixes PR5031. Unfortunately, there is no small testcase :(
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blocks and update CFG, it should also inform sdisel of the changes so the phi source operands will come from the right basic blocks.
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sdisel will use to properly complete phi nodes.
Not functionality change yet.
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Radar 7200803. (This should also fix the
SingleSource/UnitTests/Vector/sumarray-dbl test.)
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See the bug report for details.
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non-pic mode. rdar://7187172.
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makes an eggregious hack somewhat more palatable. Bringing the LSDA forward
and making it a GV available for reference would be even better, but is
beyond the scope of what I'm looking to solve at this point.
Objective C++ code could generate function names that broke the previous
scheme. This fixes that.
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Remove the assertion and generalize the code for ARM NEON stuff.
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bunch of nasty code in ARM asm printer.
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