| Age | Commit message (Expand) | Author |
|---|
| 2007-10-08 | Migrate X86 and ARM from using X86ISD::{,I}DIV and ARMISD::MULHILO{U,S} to | Dan Gohman |
| 2007-07-10 | Remove clobbersPred. Add an OptionalDefOperand to instructions which have the... | Evan Cheng |
| 2007-07-05 | Unfortunately we now require C++ code to isel Bcc, conditional moves, etc. | Evan Cheng |
| 2007-05-15 | Add PredicateOperand to all ARM instructions that have the condition field. | Evan Cheng |
| 2007-05-03 | match a reassociated form of fnmul. This implements CodeGen/ARM/fnmul.ll | Chris Lattner |
| 2007-03-19 | Fix naming inconsistencies. | Evan Cheng |
| 2007-03-19 | Special LDR instructions to load from non-pc-relative constantpools. These are | Evan Cheng |
| 2007-03-13 | AM2 can match 2^n +/- 1. e.g. ldr r3, [r2, r2, lsl #2] | Evan Cheng |
| 2007-02-07 | Get rid of references to iostream. | Evan Cheng |
| 2007-02-06 | Select add FI, c correctly. | Evan Cheng |
| 2007-02-06 | - Store val, [sp, c] must be selected to tSTRsp. | Evan Cheng |
| 2007-01-30 | Change the operand orders to t_addrmode_s* to make it easier to morph | Evan Cheng |
| 2007-01-24 | Use PC relative ldr to load from a constantpool in Thumb mode. | Evan Cheng |
| 2007-01-24 | Allow [ fi#c, imm ] as ARM load / store addresses. | Evan Cheng |
| 2007-01-24 | Various Thumb mode load / store isel bug fixes. | Evan Cheng |
| 2007-01-23 | - Reorg Thumb load / store instructions. Combine each rr and ri pair of | Evan Cheng |
| 2007-01-19 | ARM backend contribution from Apple. | Evan Cheng |
| 2007-01-12 | Build constants using instructions mov/orr or mvn/eor. | Lauro Ramos Venancio |
| 2007-01-04 | Expand SELECT (f32/f64) and FCOPYSIGN (f32/f64). | Lauro Ramos Venancio |
| 2006-12-31 | implement missing compares | Rafael Espindola |
| 2006-12-31 | For PR950: | Reid Spencer |
| 2006-12-29 | fix comment | Rafael Espindola |
| 2006-12-28 | Implement SELECT_CC (f32/f64) for ARM. | Lauro Ramos Venancio |
| 2006-12-14 | avoid using a constant table when a constant can be used inline | Rafael Espindola |
| 2006-12-12 | more general matching of the MVN instruction | Rafael Espindola |
| 2006-12-12 | don't use "ordinary" addressing mode 1 when mvn is appropriate | Rafael Espindola |
| 2006-12-12 | use MVN to handle small negative constants | Rafael Espindola |
| 2006-12-07 | What should be the last unnecessary <iostream>s in the library. | Bill Wendling |
| 2006-12-05 | expand memmove and memcpy | Rafael Espindola |
| 2006-12-05 | add support for the "r" asm constraint | Rafael Espindola |
| 2006-11-09 | implement load effective address similar to the alpha backend | Rafael Espindola |
| 2006-11-08 | Match tblegen changes. | Evan Cheng |
| 2006-11-08 | initial implementation of addressing mode 2 | Rafael Espindola |
| 2006-11-02 | move ARMCondCodeToString to ARMAsmPrinter.cpp | Rafael Espindola |
| 2006-10-30 | All targets expand BR_JT for now. | Evan Cheng |
| 2006-10-26 | initial support for frame pointers | Rafael Espindola |
| 2006-10-24 | expand ISD::VACOPY | Rafael Espindola |
| 2006-10-23 | expand ISD::MEMSET | Rafael Espindola |
| 2006-10-20 | For PR950: | Reid Spencer |
| 2006-10-19 | expand SIGN_EXTEND_INREG | Rafael Espindola |
| 2006-10-19 | expand brind so that we don't have to implement jump tables right now | Rafael Espindola |
| 2006-10-18 | implement CallingConv::Fast as CallingConv::C | Rafael Espindola |
| 2006-10-17 | expand ISD::SDIV, ISD::UDIV, ISD::SREM and ISD::UREM | Rafael Espindola |
| 2006-10-17 | initial implementation of addressing mode 5 | Rafael Espindola |
| 2006-10-16 | expand ISD::SHL_PARTS, ISD::SRA_PARTS and ISD::SRL_PARTS | Rafael Espindola |
| 2006-10-14 | expand ISD::BRCOND | Rafael Espindola |
| 2006-10-14 | fix some fp condition codes | Rafael Espindola |
| 2006-10-13 | Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode. | Evan Cheng |
| 2006-10-13 | implement calls to functions that return long | Rafael Espindola |
| 2006-10-13 | implement unordered floating point compares | Rafael Espindola |
