| Age | Commit message (Expand) | Author |
|---|
| 2010-02-22 | The predicate index isn't fixed, so scan for it to make sure we get the proper | Jim Grosbach |
| 2010-02-19 | Revert 96634. It causes assertion failures for 126.gcc and 176.gcc in | Bob Wilson |
| 2010-02-19 | Radar 7636153. In the presence of large call frames, it's not sufficient | Jim Grosbach |
| 2010-02-13 | Teach MachineFrameInfo to track maximum alignment while stack objects are being | Evan Cheng |
| 2010-02-02 | As of r79039, we still try to eliminate the frame pointer on leaf functions, | Jim Grosbach |
| 2010-01-26 | constify a method argument. | Chris Lattner |
| 2010-01-19 | For aligned load/store instructions, it's only required to know whether a | Jim Grosbach |
| 2010-01-06 | 80 column violations | Jim Grosbach |
| 2010-01-06 | Addressing mode 6 (load/store) instructions can't encode an immediate offset | Jim Grosbach |
| 2009-12-22 | Use proper move instructions. Make the verifier happy. | Jakob Stoklund Olesen |
| 2009-12-06 | Dynamic stack realignment use of sp register as source/dest register | Anton Korobeynikov |
| 2009-12-02 | Factor the stack alignment calculations out into a target independent pass. | Jim Grosbach |
| 2009-11-22 | Move default FrameReg val to getFrameIndexReference(). Otherwise, debug info ... | Jim Grosbach |
| 2009-11-22 | Generate more correct debug info for frame indices. | Jim Grosbach |
| 2009-11-21 | Revert 89562. We're being sneakier than I was giving us credit for, and this | Jim Grosbach |
| 2009-11-21 | Darwin requires a frame pointer for all non-leaf functions to support correct | Jim Grosbach |
| 2009-11-16 | Make the pass class name more explicit. | Jim Grosbach |
| 2009-11-16 | make pass name a bit more clear | Jim Grosbach |
| 2009-11-15 | Detect need for autoalignment of the stack earlier to catch spills more | Jim Grosbach |
| 2009-11-12 | Add a bool flag to StackObjects telling whether they reference spill | David Greene |
| 2009-11-09 | Now that the default is 'enabled,' a separate command line option for ARM is | Jim Grosbach |
| 2009-11-09 | Enable dynamic stack realignment by default. | Jim Grosbach |
| 2009-11-09 | Set dynamic stack realignment to real values. | Jim Grosbach |
| 2009-11-09 | Use Unified Assembly Syntax for the ARM backend. | Jim Grosbach |
| 2009-11-08 | Use aligned load/store instructions for spilling Q registers when we know the... | Jim Grosbach |
| 2009-11-04 | Grammar. | Jim Grosbach |
| 2009-11-04 | Now that the memory leak from McCat/08-main has been fixed (86056), re-enable | Jim Grosbach |
| 2009-11-04 | If a function has no stack frame at all, dynamic realignment isn't necessary. | Jim Grosbach |
| 2009-11-04 | dynamic stack realignment necessitates scanning the floating point callee- | Jim Grosbach |
| 2009-11-03 | Fix PR5367. QPR_8 is the super regclass of DPR_8 and SPR_8. | Evan Cheng |
| 2009-11-03 | Revert r85049, it is causing PR5367 | Anton Korobeynikov |
| 2009-11-01 | Make use of imm12 version of Thumb2 ldr / str instructions more aggressively. | Evan Cheng |
| 2009-10-30 | Dial back the realignment a bit. | Jim Grosbach |
| 2009-10-29 | To get more thorough testing from llc-beta nightly runs, do dynamic stack | Jim Grosbach |
| 2009-10-28 | Cleanup now that frame index scavenging via post-pass is working for ARM and ... | Jim Grosbach |
| 2009-10-27 | Enable virtual register based frame index scavenging by default for ARM & T2. | Jim Grosbach |
| 2009-10-27 | Infrastructure for dynamic stack realignment on ARM. For now, this is off by | Jim Grosbach |
| 2009-10-25 | Add ARM getMatchingSuperRegClass to handle S / D / Q cross regclass coalescing. | Evan Cheng |
| 2009-10-21 | Missing piece of the ARM frame index post-scavenging conditionalization | Jim Grosbach |
| 2009-10-21 | Conditionalize ARM/T2 frame index post-scavenging while working out fixes | Jim Grosbach |
| 2009-10-20 | Disable by default while debugging | Jim Grosbach |
| 2009-10-20 | add cmd line opt to disable frame index reuse for ARM and T2. debug aid. | Jim Grosbach |
| 2009-10-20 | Enable post-pass frame index register scavenging for ARM and Thumb2 | Jim Grosbach |
| 2009-10-19 | Enable allocation of R3 in Thumb1 | Jim Grosbach |
| 2009-10-07 | Add register-reuse to frame-index register scavenging. When a target uses | Jim Grosbach |
| 2009-10-05 | In Thumb1, the register scavenger is not always able to use an emergency | Jim Grosbach |
| 2009-09-30 | Clarify comment phrasing. | Jim Grosbach |
| 2009-09-30 | When checking whether we need to reserve a register for the scavenger, | Jim Grosbach |
| 2009-09-29 | minor cleanup and add clarifying comment | Jim Grosbach |
| 2009-09-28 | Adjust processFunctionBeforeCalleeSavedScan() to correctly reserve a stack | Jim Grosbach |
