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AgeCommit message (Expand)Author
2010-06-24Remove the now unused LiveIntervals::getVNInfoSourceReg().Jakob Stoklund Olesen
2010-06-24Teach AdjustCopiesBackFrom to also use CoalescerPair to identify compatible c...Jakob Stoklund Olesen
2010-06-24Remove the -fast-spill option.Jakob Stoklund Olesen
2010-06-24Loosen up the requirements in the Horrible Hack(tm) to include all selectorsBill Wendling
2010-06-24Replace a big gob of old coalescer logic with the new CoalescerPair class.Jakob Stoklund Olesen
2010-06-24Print the LSBs of a SlotIndex symbolically using letters referring to theJakob Stoklund Olesen
2010-06-24Simplify this code; switch lowering shouldn't produce casesDan Gohman
2010-06-24Be more strict about subreg-to-subreg copies in CoalescerPair.Jakob Stoklund Olesen
2010-06-24Verify that VNI kills are pointing to existing instructions.Jakob Stoklund Olesen
2010-06-24Eliminate the other half of the BRCOND optimization, and updateDan Gohman
2010-06-24Eliminate the first have of the optimization which eliminates BRCONDDan Gohman
2010-06-24Reapply r106634, now that the bug it exposed is fixed.Dan Gohman
2010-06-24Optimize the "bit test" code path for switch lowering in theDan Gohman
2010-06-24Revert "Replace a big gob of old coalescer logic with the new CoalescerPair c...Jakob Stoklund Olesen
2010-06-24Replace a big gob of old coalescer logic with the new CoalescerPair class.Jakob Stoklund Olesen
2010-06-23MorphNodeTo doesn't preserve the memory operands. Because we're morphing a nodeBill Wendling
2010-06-23Revert r106263, "Fold the ShrinkDemandedOps pass into the regular DAGCombiner...Daniel Dunbar
2010-06-23Some targets don't require the fencing MEMBARRIER instructions surroundingJim Grosbach
2010-06-23Add a few VNInfo data structure checks.Jakob Stoklund Olesen
2010-06-23Revert r106066, "Create a more targeted fix for not sinking instructions into...Daniel Dunbar
2010-06-22Also convert SUBREG_TO_REG to a KILL when relevant, like the other subregJakob Stoklund Olesen
2010-06-22Move PHIElimination's SplitCriticalEdge for MachineBasicBlocks outDan Gohman
2010-06-22Remove the SimpleJoin optimization from SimpleRegisterCoalescing.Jakob Stoklund Olesen
2010-06-22Use pre-increment instead of post-increment when the result is not used.Dan Gohman
2010-06-22When unfolding a load, avoid assuming which instruction thatDan Gohman
2010-06-22Use single interface, using twine, to get named metadata.Devang Patel
2010-06-22Tail merging pass shall not break up IT blocks. rdar://8115404Evan Cheng
2010-06-22Discard special LLVM prefix from linkage name.Devang Patel
2010-06-22Do not rely on Twine temporaries to survive.Devang Patel
2010-06-22Fix the new load-unfolding code to update LiveVariable's dead flags,Dan Gohman
2010-06-21Teach two-address lowering how to unfold a load to open up commutingDan Gohman
2010-06-21Use A.append(...) instead of A.insert(A.end(), ...) when A is aDan Gohman
2010-06-21Revert r106422, which is breaking the non-fast-isel path.Dan Gohman
2010-06-21More changes for non-top-down fast-isel.Dan Gohman
2010-06-21Do one lookup instead of two.Dan Gohman
2010-06-21Generalize this to look in the regular ValueMap in addition toDan Gohman
2010-06-19Tidy.Bob Wilson
2010-06-18Teach regular and fast isel to set dead flags on unused implicit defsDan Gohman
2010-06-18Only run CoalesceExtSubRegs when we can expect LiveIntervalAnalysis to clean upJakob Stoklund Olesen
2010-06-18Allow ARM if-converter to be run after post allocation scheduling.Evan Cheng
2010-06-18back-end libcall handling for ATOMIC_SWAP (__sync_lock_test_and_set)Jim Grosbach
2010-06-18TwoAddressInstructionPass::CoalesceExtSubRegs can insert INSERT_SUBREGJakob Stoklund Olesen
2010-06-18Fix an inverted condition.Evan Cheng
2010-06-18Fix cross initialization compilation error.Evan Cheng
2010-06-18Teach iff-converter to properly count # of dups. It was not skipping over dbg...Evan Cheng
2010-06-18Add Expand-to-libcall support for additional atomics. This covers the usualJim Grosbach
2010-06-18Don't leak RegClass2VRegMap, which is now a new[] array instead of aDan Gohman
2010-06-18Start TargetRegisterClass indices at 0 instead of 1, so thatDan Gohman
2010-06-18Fix PR7372: Conditional branches (at least on ARM) are treated as predicated,Bob Wilson
2010-06-18Don't bother calling releaseMemory before destroying the DominatorTreeBase.Dan Gohman