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2012-03-27fix what looks like a real logic bug, found by PVS-Studio (part of PR12357)Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153513 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-26Add a debug statement.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153428 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-24Add the ability to promote legal integer VAARGs. This is required for the ↵Hal Finkel
PPC64 SVR4 ABI. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153372 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-22Source order scheduler should not preschedule nodes with multiple uses. ↵Evan Cheng
rdar://11096639 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153270 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-22Assign node orders to target intrinsics which do not produce results. ↵Evan Cheng
rdar://11096639 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153269 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-22[fast-isel] Fold "urem x, pow2" -> "and x, pow2-1". This should fix the 271%Chad Rosier
execution-time regression for nsieve-bits on the ARMv7 -O0 -g nightly tester. This may also improve compile-time on architectures that would otherwise generate a libcall for urem (e.g., ARM) or fall back to the DAG selector. rdar://10810716 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153230 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-21Checking a build_vector for an all-ones value.Jim Grosbach
Type legalization can zero-extend the elements of the build_vector node, so, for example, we may have an <8 x i8> with i32 elements of value 255. That should return 'true' for the vector being all ones. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153203 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20When combining (vextract shuffle (load ), <1,u,u,u>), 0) -> (load ), add ↵Craig Topper
users of the final load to the worklist too. Needed by changes I'm preparing to make to X86 backend. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153078 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20Do everything up to generating code to try to get a register forEric Christopher
a variable. The previous code would break the debug info changing code invariant. This will regress debug info for arguments where we elide the alloca created. Fixes rdar://11066468 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153074 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20Untabify.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153073 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20Add another debugging statement here.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153072 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-20Use lookUpRegForValue here instead of duplicating the code.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153071 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-19f16 FDIV can now be legalized by promoting to f32Pete Cooper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153064 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-19Fix DAG combine which creates illegal vector shuffles. Patch by Heikki Kultala.Duncan Sands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153035 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-16Revert r152613 (and r152614), "Inline the d'tor and add an anchor instead." ↵NAKAMURA Takumi
for workaround of g++-4.4's miscompilation. It caused MSP430DAGToDAGISel::SelectIndexedBinOp() to be miscompiled. When two ReplaceUses()'s are expanded as inline, vtable in base class is stored to latter (ISelUpdater)ISU. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152877 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-15We actually handle AllocaInst via getRegForValue below just fine.Eric Christopher
Part of rdar://8905263 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152845 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-15Add some debugging output into fast isel as well.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152844 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-15Add another debug statement.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152843 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-15When optimizing certain BUILD_VECTOR nodes into other BUILD_VECTOR nodes, ↵Nadav Rotem
add the new node into the work list because there is a potential for further optimizations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152784 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-15Add a xform to the DAG combiner.Bill Wendling
Transform: (fsub x, (fadd x, y)) -> (fneg y) and (fsub x, (fadd y, x)) -> (fneg y) if 'unsafe math' is specified. <rdar://problem/7540295> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152777 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-14Insert the debugging instructions in one fell-swoop so that it doesn't call theBill Wendling
expensive "getFirstTerminator" call. This reduces the time of compilation in PR12258 from >10 minutes to < 10 seconds. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152704 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-13Fortify r152675 a bit. Although I'm not able to come up with a test case ↵Evan Cheng
that would trigger the truncation case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152678 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-13DAG combine incorrectly optimize (i32 vextract (v4i16 load $addr), c) toEvan Cheng
(i16 load $addr+c*sizeof(i16)) and replace uses of (i32 vextract) with the i16 load. It should issue an extload instead: (i32 extload $addr+c*sizeof(i16)). rdar://11035895 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152675 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-13Add a return type.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152614 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-13Inline the d'tor and add an anchor instead.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152613 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-13Refactor the SelectionDAG's 'dump' methods into their own .cpp file.Bill Wendling
No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152611 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-11llvm::SwitchInstStepan Dyatkovskiy
Renamed methods caseBegin, caseEnd and caseDefault with case_begin, case_end, and case_default. Added some notes relative to case iterators. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152532 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-10Give dagcombiner's worklist some inline capacity.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152454 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-08Use uint16_t to store instruction implicit uses and defs. Reduces static data.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152301 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-08Taken into account Duncan's comments for r149481 dated by 2nd Feb 2012:Stepan Dyatkovskiy
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20120130/136146.html Implemented CaseIterator and it solves almost all described issues: we don't need to mix operand/case/successor indexing anymore. Base iterator class is implemented as a template since it may be initialized either from "const SwitchInst*" or from "SwitchInst*". ConstCaseIt is just a read-only iterator. CaseIt is read-write iterator; it allows to change case successor and case value. Usage of iterator allows totally remove resolveXXXX methods. All indexing convertions done automatically inside the iterator's getters. Main way of iterator usage looks like this: SwitchInst *SI = ... // intialize it somehow for (SwitchInst::CaseIt i = SI->caseBegin(), e = SI->caseEnd(); i != e; ++i) { BasicBlock *BB = i.getCaseSuccessor(); ConstantInt *V = i.getCaseValue(); // Do something. } If you want to convert case number to TerminatorInst successor index, just use getSuccessorIndex iterator's method. If you want initialize iterator from TerminatorInst successor index, use CaseIt::fromSuccessorIndex(...) method. There are also related changes in llvm-clients: klee and clang. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152297 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07misched preparation: rename core scheduler methods for consistency.Andrew Trick
We had half the API with one convention, half with another. Now was a good time to clean it up. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152255 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07misched preparation: clarify ScheduleDAG and ScheduleDAGInstrs roles.Andrew Trick
ScheduleDAG is responsible for the DAG: SUnits and SDeps. It provides target hooks for latency computation. ScheduleDAGInstrs extends ScheduleDAG and defines the current scheduling region in terms of MachineInstr iterators. It has access to the target's scheduling itinerary data. ScheduleDAGInstrs provides the logic for building the ScheduleDAG for the sequence of MachineInstrs in the current region. Target's can implement highly custom schedulers by extending this class. ScheduleDAGPostRATDList provides the driver and diagnostics for current postRA scheduling. It maintains a current Sequence of scheduled machine instructions and logic for splicing them into the block. During scheduling, it uses the ScheduleHazardRecognizer provided by the target. Specific changes: - Removed driver code from ScheduleDAG. clearDAG is the only interface needed. - Added enterRegion/exitRegion hooks to ScheduleDAGInstrs to delimit the scope of each scheduling region and associated DAG. They should be used to setup and cleanup any region-specific state in addition to the DAG itself. This is necessary because we reuse the same ScheduleDAG object for the entire function. The target may extend these hooks to do things at regions boundaries, like bundle terminators. The hooks are called even if we decide not to schedule the region. So all instructions in a block are "covered" by these calls. - Added ScheduleDAGInstrs::begin()/end() public API. - Moved Sequence into the driver layer, which is specific to the scheduling algorithm. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152208 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07misched preparation: modularize schedule emission.Andrew Trick
ScheduleDAG has nothing to do with how the instructions are scheduled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152206 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07misched preparation: modularize schedule printing.Andrew Trick
ScheduleDAG will not refer to the scheduled instruction sequence. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152205 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07misched preparation: modularize schedule verification.Andrew Trick
ScheduleDAG will not refer to the scheduled instruction sequence. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152204 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07whitespaceAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152203 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07Cleanup in preparation for misched: Move DAG visualization logic.Andrew Trick
Soon, ScheduleDAG will not refer to the BB. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152177 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07whitespaceAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152175 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-07Cleanup: DAG building is specific to either SD or MI scheduling. Not part of ↵Andrew Trick
the target interface. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152174 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06Extend r148086 to check for [r +/- reg] address mode. This fixes queens ↵Evan Cheng
performance regression (due to increased register pressure from overly aggressive pre-inc formation). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152162 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-06Make it possible for a target to mark FSUB as Expand. This requires ↵Owen Anderson
providing a default expansion (FADD+FNEG), and teaching DAGCombine not to form FSUBs post-legalize if they are not legal. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152079 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-05Fix warnings about adding a bool to a string.Bill Wendling
Patch by Sean Silva! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152042 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-04Use uint16_t to store register overlaps to reduce static data.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152001 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-01Fix a codegen fault in which log2 or exp2 could be dead-code eliminated even ↵James Molloy
though they could have sideeffects. Only allow log2/exp2 to be converted to an intrinsic if they are declared "readnone". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151807 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-29LegalizeIntegerTypes: Reorder operations in the "big shift by small amount" ↵Benjamin Kramer
optimization, making the lives of later passes easier. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151722 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-28Re-commit r151623 with fix. Only issue special no-return calls if it's a ↵Evan Cheng
direct call. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151645 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-28Fix off-by one in comment.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151644 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-28LegalizeIntegerTypes: Reenable the large shift with small amount optimization.Benjamin Kramer
To avoid problems with zero shifts when getting the bits that move between words we use a trick: first shift the by amount-1, then do another shift by one. When amount is 0 (and size 32) we first shift by 31, then by one, instead of by 32. Also fix a latent bug that emitted the low and high words in the wrong order when shifting right. Fixes PR12113. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151637 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-28Revert r151623 "Some ARM implementaions, e.g. A-series, does return stack ↵Daniel Dunbar
prediction. ...", it is breaking the Clang build during the Compiler-RT part. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151630 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-28Code cleanup following CR by Duncan.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151627 91177308-0d34-0410-b5e6-96231b3b80d8
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