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path: root/lib/CodeGen/SelectionDAG
AgeCommit message (Expand)Author
2007-04-05Change the bit_part_select (non)implementation from "return 0" to abort.Reid Spencer
2007-04-04Implement the llvm.bit.part_select.iN.iN.iN overloaded intrinsic.Reid Spencer
2007-04-04Properly emit range comparisons for switch cases, where neighbour casesAnton Korobeynikov
2007-04-021. Insert custom lowering hooks for ISD::ROTR and ISD::ROTL.Scott Michel
2007-04-01For PR1297:Reid Spencer
2007-04-01For PR1297:Reid Spencer
2007-03-31move a bunch of code out of the sdisel pass into its own opt pass "codegenpre...Chris Lattner
2007-03-31switch TL::getValueType to use MVT::getValueType.Chris Lattner
2007-03-30add one addressing mode description hook to rule them all.Chris Lattner
2007-03-30Fix incorrect combination of different loads. Reenable zext-over-truncateDale Johannesen
2007-03-29Disable load width reduction xform of variant (zext (truncate load x)) forEvan Cheng
2007-03-28Scale 1 is always ok.Evan Cheng
2007-03-28Remove isLegalAddressImmediate.Evan Cheng
2007-03-28GEP index sinking fixes:Evan Cheng
2007-03-27Remove dead codeAnton Korobeynikov
2007-03-27Split big monster into small helpers. No functionality change.Anton Korobeynikov
2007-03-27SDISel does not preserve all, it changes CFG and other info.Evan Cheng
2007-03-26SIGN_EXTEND_INREG requires one extra operand, a ValueType node.Evan Cheng
2007-03-25First step of switch lowering refactoring: perform worklist-drivenAnton Korobeynikov
2007-03-25Implement support for vector operands to inline asm, implementingChris Lattner
2007-03-25implement initial support for the silly X constraint. Testcase here: CodeGen...Chris Lattner
2007-03-25Implement CodeGen/X86/2007-03-24-InlineAsmMultiRegConstraint.llChris Lattner
2007-03-25switch TargetLowering::getConstraintType to take the entire constraint,Chris Lattner
2007-03-24don't rely on ADLChris Lattner
2007-03-24Adjust offset to compensate for big endian machines.Evan Cheng
2007-03-23Make sure SEXTLOAD of the specific type is supported on the target.Evan Cheng
2007-03-23Also replace uses of SRL if that's also folded during ReduceLoadWidth().Evan Cheng
2007-03-23A couple of bug fixes for reducing load width xform:Evan Cheng
2007-03-22Change uses of Function::front to Function::getEntryBlock for readability.Dan Gohman
2007-03-22More opportunities to reduce load size.Evan Cheng
2007-03-21repair x86 performance, dejagnu problems from previous changeDale Johannesen
2007-03-21fold (truncate (srl (load x), c)) -> (smaller load (x+c/vt bits))Evan Cheng
2007-03-20do not share old induction variables when this would result in invalidDale Johannesen
2007-03-20Fix some VC++ warnings.Jeff Cohen
2007-03-20Code clean up.Lauro Ramos Venancio
2007-03-20Minor bug.Evan Cheng
2007-03-20CopyToReg source operand can be a physical register.Lauro Ramos Venancio
2007-03-17Use SmallSet instead of std::set.Evan Cheng
2007-03-17If sdisel has decided to sink GEP index expression into any BB. Replace all usesEvan Cheng
2007-03-16Turn on GEP index sinking by default.Evan Cheng
2007-03-16Stupid bug.Evan Cheng
2007-03-16Sink a binary expression into its use blocks if it is a loop invariantEvan Cheng
2007-03-16Added isLegalAddressExpression hook to test if the given expression can beEvan Cheng
2007-03-14Estimate a cost using the possible number of scratch registers required and useEvan Cheng
2007-03-13Try schedule def + use closer whne Sethi-Ullman numbers are the same.Evan Cheng
2007-03-12More flexible TargetLowering LSR hooks for testing whether an immediate is a ...Evan Cheng
2007-03-08implement support for floating point constants used as inline asm memory oper...Chris Lattner
2007-03-08make this fail even in non-assert builds.Chris Lattner
2007-03-07Refactoring of formal parameter flags. Enable properly use ofAnton Korobeynikov
2007-03-07Avoid combining indexed load further.Evan Cheng
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