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2011-04-13During post-legalization DAG combining, be careful to only create shifts ↵Owen Anderson
where the RHS is of the legal type for the new operation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129484 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-13Recommit r129383. PreRA scheduler heuristic fixes: VRegCycle, TokenFactor ↵Andrew Trick
latency. Additional fixes: Do something reasonable for subtargets with generic itineraries by handle node latency the same as for an empty itinerary. Now nodes default to unit latency unless an itinerary explicitly specifies a zero cycle stage or it is a TokenFactor chain. Original fixes: UnitsSharePred was a source of randomness in the scheduler: node priority depended on the queue data structure. I rewrote the recent VRegCycle heuristics to completely replace the old heuristic without any randomness. To make the ndoe latency adjustments work, I also needed to do something a little more reasonable with TokenFactor. I gave it zero latency to its consumers and always schedule it as low as possible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129421 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-12Revert 129383. It causes some targets to hit a scheduler assert.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129385 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-12PreRA scheduler heuristic fixes: VRegCycle, TokenFactor latency.Andrew Trick
UnitsSharePred was a source of randomness in the scheduler: node priority depended on the queue data structure. I rewrote the recent VRegCycle heuristics to completely replace the old heuristic without any randomness. To make these heuristic adjustments to node latency work, I also needed to do something a little more reasonable with TokenFactor. I gave it zero latency to its consumers and always schedule it as low as possible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129383 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-11Don't include Operator.h from InstrTypes.h.Jay Foad
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129271 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-09Avoid excess precision issues that lead to generating host-compiler-specific ↵Chris Lattner
code. Switch lowering probably shouldn't be using FP for this. This resolves PR9581. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129199 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-09have dag combine zap "store undef", which can be formed during call loweringChris Lattner
with undef arguments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129185 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-08Change -arm-trap-func= into a non-arm specific option. Now Intrinsic::trap ↵Evan Cheng
is lowered into a call to the specified trap function at sdisel time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129152 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-07Added a check in the preRA scheduler for potential interference on aAndrew Trick
induction variable. The preRA scheduler is unaware of induction vars, so we look for potential "virtual register cycles" instead. Fixes <rdar://problem/8946719> Bad scheduling prevents coalescing git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129100 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05Revamp the SjLj "dispatch setup" intrinsic.Bill Wendling
It needed to be moved closer to the setjmp statement, because the code directly after the setjmp needs to know about values that are on the stack. Also, the 'bitcast' of the function context was causing a dead load. This wouldn't be too horrible, except that at -O0 it wasn't optimized out, and because it wasn't using the correct base pointer (if there is a VLA), it would try to access a value from a garbage address. <rdar://problem/9130540> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128873 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-05Revert 123704; it broke threaded LLVM.Stuart Hastings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128868 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-02Add a RemoveFromWorklist method to DCI. This is needed to do some complicatedCameron Zwarich
transformations in target-specific DAG combines without causing DAGCombiner to delete the same node twice. If you know of a better way to avoid this (see my next patch for an example), please let me know. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128758 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-01Add comments.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128730 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-01Assign node order numbers to results of call instruction lowering. This ↵Evan Cheng
should improve src line debug info when sdisel is used. rdar://9199118 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128728 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-01Issue libcalls __udivmod*i4 / __divmod*i4 for div / rem pairs.Evan Cheng
rdar://8911343 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128696 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-26Turn SelectionDAGBuilder::GetRegistersForValue into a local function.Benjamin Kramer
It couldn't be used outside of the file because SDISelAsmOperandInfo is local to SelectionDAGBuilder.cpp. Making it a static function avoids a weird linkage dance. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128342 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-25Fix for -pre-RA-sched=source.Andrew Trick
Yet another case of unchecked NULL node (for physreg copy). May fix PR9509. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128266 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-23PR9535: add support for splitting and scalarizing vector ISD::FP_ROUND.Eli Friedman
Also cleaning up some duplicated code while I'm here. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128176 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-23Ensure that def-side physreg copies are scheduled above any other usesAndrew Trick
so the scheduler can't create new interferences on the copies themselves. Prior to this fix the scheduler could get stuck in a loop creating copies. Fixes PR9509. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128164 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-23whitespaceAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128163 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-23Added block number and name to isel debug output.Andrew Trick
I'm tired of doing this manually for each checkout. If anyone knows a better way debug isel for non-trivial tests feel free to revert and let me know how to do it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128132 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-21Grammar-o.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128004 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-19Add support for legalizing UINT_TO_FP of vectors on platforms which doNadav Rotem
not have native support for this operation (such as X86). The legalized code uses two vector INT_TO_FP operations and is faster than scalarizing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127951 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-17BuildUDIV: If the divisor is even we can simplify the fixup of the ↵Benjamin Kramer
multiplied value by introducing an early shift. This allows us to compile "unsigned foo(unsigned x) { return x/28; }" into shrl $2, %edi imulq $613566757, %rdi, %rax shrq $32, %rax ret instead of movl %edi, %eax imulq $613566757, %rax, %rcx shrq $32, %rcx subl %ecx, %eax shrl %eax addl %ecx, %eax shrl $4, %eax on x86_64 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127829 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-17Move more logic into getTypeForExtArgOrReturn.Cameron Zwarich
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127809 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-17Rename getTypeForExtendedInteger() to getTypeForExtArgOrReturn().Cameron Zwarich
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127807 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-16The x86-64 ABI says that a bool is only guaranteed to be sign-extended to a byteCameron Zwarich
rather than an int. Thankfully, this only causes LLVM to miss optimizations, not generate incorrect code. This just fixes the zext at the return. We still insert an i32 ZextAssert when reading a function's arguments, but it is followed by a truncate and another i8 ZextAssert so it is not optimized. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127766 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-16Don't recompute something that we already have in a local variable.Cameron Zwarich
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127764 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15sext(undef) = 0, because the top bits will all be the same.Evan Cheng
zext(undef) = 0, because the top bits will be zero. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127649 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-14BIT_CONVERT has been renamed to BITCAST.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127600 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-14Minor optimization. sign-ext/anyext of undef is still undef.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127598 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11Teach FastISel to support register-immediate-immediate instructions.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127496 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11Replace -dag-chain-limit flag with constant. It has survived a release cycle ↵Andrew Trick
without being touched, so no longer needs to pollute the hidden-help text. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127468 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-11Avoid replacing the value of a directly stored load with the stored value if ↵Evan Cheng
the load is indexed. rdar://9117613. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127440 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-10Re-commit 127368 and 127371. They are exonerated.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127380 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-09Revert 127368 and 127371 for now.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127376 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-09Change the definition of TargetRegisterInfo::getCrossCopyRegClass to be moreEvan Cheng
flexible. If it returns a register class that's different from the input, then that's the register class used for cross-register class copies. If it returns a register class that's the same as the input, then no cross- register class copies are needed (normal copies would do). If it returns null, then it's not at all possible to copy registers of the specified register class. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127368 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-09Improve pre-RA-sched register pressure tracking for duplicate operands.Andrew Trick
This helps cases like 2008-07-19-movups-spills.ll, but doesn't have an obvious impact on benchmarks git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127347 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-09Fix typo, make helper static.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127335 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-08Fix some latent bugs if the nodes are unschedulable. We'd gotten awayEric Christopher
with this before since none of the register tracking or nightly tests had unschedulable nodes. This should probably be refixed with a special default Node that just returns some "don't touch me" values. Fixes PR9427 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127263 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-08Further improvements to pre-RA-sched=list-ilp.Andrew Trick
This change uses the MaxReorderWindow for both height and depth, which tends to limit the negative effects of high register pressure. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127203 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-07Move getRegPressureLimit() from TargetLoweringInfo to TargetRegisterInfo.Cameron Zwarich
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127175 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-07Use the correct LHS type when determining the legalization of a shift's RHS ↵Owen Anderson
type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127163 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-06Typo.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127131 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-06Disable a couple of experimental heuristics to get the best results from the ↵Andrew Trick
current implementation of -pre-RA-sched=list-ilp. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127113 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-05Be explicit with abs(). Visual Studio workaround.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127075 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-05Fix for -sched-high-latency-cycles in sched=list-ilp mode.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127071 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-05Missing comment.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127068 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-05Increased the register pressure limit on x86_64 from 8 to 12Andrew Trick
regs. This is the only change in this checkin that may affects the default scheduler. With better register tracking and heuristics, it doesn't make sense to artificially lower the register limit so much. Added -sched-high-latency-cycles and X86InstrInfo::isHighLatencyDef to give the scheduler a way to account for div and sqrt on targets that don't have an itinerary. It is currently defaults to 10 (the actual number doesn't matter much), but only takes effect on non-default schedulers: list-hybrid and list-ilp. Added several heuristics that can be individually disabled for the non-default sched=list-ilp mode. This helps us determine how much better we can do on a given benchmark than the default scheduler. Certain compute intensive loops run much faster in this mode with the right set of heuristics, and it doesn't seem to have much negative impact elsewhere. Not all of the heuristics are needed, but we still need to experiment to decide which should be disabled by default for sched=list-ilp. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127067 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-04Revert commit 126684 "Use the correct shift amount type". It is only the ↵Duncan Sands
correct type after type legalization has completed. Before then it may simply not be big enough to hold the shift amount, particularly on x86 which uses a very small type for shifts (this issue broke stuff in the past which is why LegalizeTypes carefully uses a large type for shift amounts). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127000 91177308-0d34-0410-b5e6-96231b3b80d8
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