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path: root/lib/CodeGen/SelectionDAG
AgeCommit message (Expand)Author
2011-04-13During post-legalization DAG combining, be careful to only create shifts wher...Owen Anderson
2011-04-13Recommit r129383. PreRA scheduler heuristic fixes: VRegCycle, TokenFactor lat...Andrew Trick
2011-04-12Revert 129383. It causes some targets to hit a scheduler assert.Andrew Trick
2011-04-12PreRA scheduler heuristic fixes: VRegCycle, TokenFactor latency.Andrew Trick
2011-04-11Don't include Operator.h from InstrTypes.h.Jay Foad
2011-04-09Avoid excess precision issues that lead to generating host-compiler-specific ...Chris Lattner
2011-04-09have dag combine zap "store undef", which can be formed during call loweringChris Lattner
2011-04-08Change -arm-trap-func= into a non-arm specific option. Now Intrinsic::trap is...Evan Cheng
2011-04-07Added a check in the preRA scheduler for potential interference on aAndrew Trick
2011-04-05Revamp the SjLj "dispatch setup" intrinsic.Bill Wendling
2011-04-05Revert 123704; it broke threaded LLVM.Stuart Hastings
2011-04-02Add a RemoveFromWorklist method to DCI. This is needed to do some complicatedCameron Zwarich
2011-04-01Add comments.Evan Cheng
2011-04-01Assign node order numbers to results of call instruction lowering. This shoul...Evan Cheng
2011-04-01Issue libcalls __udivmod*i4 / __divmod*i4 for div / rem pairs.Evan Cheng
2011-03-26Turn SelectionDAGBuilder::GetRegistersForValue into a local function.Benjamin Kramer
2011-03-25Fix for -pre-RA-sched=source.Andrew Trick
2011-03-23PR9535: add support for splitting and scalarizing vector ISD::FP_ROUND.Eli Friedman
2011-03-23Ensure that def-side physreg copies are scheduled above any other usesAndrew Trick
2011-03-23whitespaceAndrew Trick
2011-03-23Added block number and name to isel debug output.Andrew Trick
2011-03-21Grammar-o.Eric Christopher
2011-03-19Add support for legalizing UINT_TO_FP of vectors on platforms which doNadav Rotem
2011-03-17BuildUDIV: If the divisor is even we can simplify the fixup of the multiplied...Benjamin Kramer
2011-03-17Move more logic into getTypeForExtArgOrReturn.Cameron Zwarich
2011-03-17Rename getTypeForExtendedInteger() to getTypeForExtArgOrReturn().Cameron Zwarich
2011-03-16The x86-64 ABI says that a bool is only guaranteed to be sign-extended to a byteCameron Zwarich
2011-03-16Don't recompute something that we already have in a local variable.Cameron Zwarich
2011-03-15sext(undef) = 0, because the top bits will all be the same.Evan Cheng
2011-03-14BIT_CONVERT has been renamed to BITCAST.Evan Cheng
2011-03-14Minor optimization. sign-ext/anyext of undef is still undef.Evan Cheng
2011-03-11Teach FastISel to support register-immediate-immediate instructions.Owen Anderson
2011-03-11Replace -dag-chain-limit flag with constant. It has survived a release cycle ...Andrew Trick
2011-03-11Avoid replacing the value of a directly stored load with the stored value if ...Evan Cheng
2011-03-10Re-commit 127368 and 127371. They are exonerated.Evan Cheng
2011-03-09Revert 127368 and 127371 for now.Evan Cheng
2011-03-09Change the definition of TargetRegisterInfo::getCrossCopyRegClass to be moreEvan Cheng
2011-03-09Improve pre-RA-sched register pressure tracking for duplicate operands.Andrew Trick
2011-03-09Fix typo, make helper static.Benjamin Kramer
2011-03-08Fix some latent bugs if the nodes are unschedulable. We'd gotten awayEric Christopher
2011-03-08Further improvements to pre-RA-sched=list-ilp.Andrew Trick
2011-03-07Move getRegPressureLimit() from TargetLoweringInfo to TargetRegisterInfo.Cameron Zwarich
2011-03-07Use the correct LHS type when determining the legalization of a shift's RHS t...Owen Anderson
2011-03-06Typo.Eric Christopher
2011-03-06Disable a couple of experimental heuristics to get the best results from the ...Andrew Trick
2011-03-05Be explicit with abs(). Visual Studio workaround.Andrew Trick
2011-03-05Fix for -sched-high-latency-cycles in sched=list-ilp mode.Andrew Trick
2011-03-05Missing comment.Andrew Trick
2011-03-05Increased the register pressure limit on x86_64 from 8 to 12Andrew Trick
2011-03-04Revert commit 126684 "Use the correct shift amount type". It is only the cor...Duncan Sands
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