| Age | Commit message (Expand) | Author |
|---|
| 2012-01-14 | misched: Initial code for building an MI level scheduling DAG | Andrew Trick |
| 2012-01-14 | Move physreg dependency generation into aptly named addPhysRegDeps. | Andrew Trick |
| 2012-01-14 | misched: Added ScheduleDAGInstrs::IsPostRA | Andrew Trick |
| 2012-01-07 | Added a late machine instruction copy propagation pass. This catches | Evan Cheng |
| 2012-01-05 | Remove an unused variable. | Chandler Carruth |
| 2012-01-05 | Minor postra scheduler cleanup. It could result in more precise antidependenc... | Andrew Trick |
| 2011-12-14 | Model ARM predicated write as read-mod-write. e.g. | Evan Cheng |
| 2011-12-14 | Allow target to specify register output dependency. Still default to one. | Evan Cheng |
| 2011-12-14 | - Add MachineInstrBundle.h and MachineInstrBundle.cpp. This includes a function | Evan Cheng |
| 2011-12-07 | Add bundle aware API for querying instruction properties and switch the code | Evan Cheng |
| 2011-12-06 | First chunk of MachineInstr bundle support. | Evan Cheng |
| 2011-12-02 | make sure ScheduleDAGInstrs::EmitSchedule does not crash when the first instr... | Hal Finkel |
| 2011-10-07 | PostRA scheduler fix. Clear stale loop dependencies. | Andrew Trick |
| 2011-10-07 | whitespace | Andrew Trick |
| 2011-07-01 | Rename TargetSubtarget to TargetSubtargetInfo for consistency. | Evan Cheng |
| 2011-06-29 | Sink SubtargetFeature and TargetInstrItineraries (renamed MCInstrItineraries)... | Evan Cheng |
| 2011-06-28 | - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and | Evan Cheng |
| 2011-06-02 | Remove dead code. | Devang Patel |
| 2011-06-02 | Update DBG_VALUEs while breaking anti dependencies. | Devang Patel |
| 2011-06-02 | During post RA scheduling, do not try to chase reg defs. to preserve DBG_VALU... | Devang Patel |
| 2011-05-06 | Added an assertion, and updated a comment. | Andrew Trick |
| 2011-05-05 | ARM post RA scheduler compile time fix. | Andrew Trick |
| 2011-05-05 | whitespace | Andrew Trick |
| 2011-04-15 | Fix a ton of comment typos found by codespell. Patch by | Chris Lattner |
| 2011-01-07 | Do not model all INLINEASM instructions as having unmodelled side effects. | Evan Cheng |
| 2010-12-15 | Move Value::getUnderlyingObject to be a standalone | Dan Gohman |
| 2010-11-03 | Two sets of changes. Sorry they are intermingled. | Evan Cheng |
| 2010-10-27 | Putting r117193 back except for the compile time cost. Rather than assuming f... | Evan Cheng |
| 2010-10-25 | Neuter r117193 as it causes significant post-ra scheduler compile time regres... | Evan Cheng |
| 2010-10-23 | Properly model the latency of register defs which are 1) function returns or | Evan Cheng |
| 2010-10-08 | Avoid compiler warning: comparison between signed and unsigned integer. | Evan Cheng |
| 2010-10-08 | Fix operand latency computation in cases where the definition operand is | Evan Cheng |
| 2010-10-06 | Remove unused variables. | Nick Lewycky |
| 2010-10-06 | - Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This | Evan Cheng |
| 2010-09-29 | Model Cortex-a9 load to SUB, RSB, ADD, ADC, SBC, RSC, CMN, MVN, or CMP | Evan Cheng |
| 2010-09-10 | Teach if-converter to be more careful with predicating instructions that would | Evan Cheng |
| 2010-07-24 | Change ScheduleDAGInstrs::Defs and ::Uses to be variable-size vectors | Bob Wilson |
| 2010-07-15 | Use std::vector instead of TargetRegisterInfo::FirstVirtualRegister. | Bill Wendling |
| 2010-05-19 | Fix the post-RA instruction scheduler to handle instructions referenced by | Jim Grosbach |
| 2010-05-01 | Get rid of the EdgeMapping map. Instead, just check for BasicBlock | Dan Gohman |
| 2010-04-17 | Fix -Wcast-qual warnings. | Dan Gohman |
| 2010-03-22 | Reduce indentation. | Evan Cheng |
| 2010-03-22 | 80 col violation. | Evan Cheng |
| 2010-03-10 | Progress towards shepherding debug info through SelectionDAG. | Dale Johannesen |
| 2010-02-16 | There are two ways of checking for a given type, for example isa<PointerType>(T) | Duncan Sands |
| 2009-11-09 | Fix dependencies added to model memory aliasing for post-RA scheduling. The d... | David Goodwin |
| 2009-11-05 | Correctly add chain dependencies around calls and unknown-side-effect instruc... | David Goodwin |
| 2009-11-03 | <rdar://problem/7352605>. When building schedule graph use mayAlias informati... | David Goodwin |
| 2009-11-02 | Chain dependencies used to enforce memory order should have latency of 0 (exc... | David Goodwin |
| 2009-10-26 | When checking whether a def of an aliased register is dead, ask the | Dan Gohman |
