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path: root/lib/CodeGen/ScheduleDAGInstrs.cpp
AgeCommit message (Expand)Author
2012-11-15Fix indeterminism in MI scheduler DAG construction.Sergei Larin
2012-11-12misched: Infrastructure for weak DAG edges.Andrew Trick
2012-11-06ScheduleDAG interface. Added OrderKind to distinguish nonregister dependencies.Andrew Trick
2012-10-30[inline asm] Implement mayLoad and mayStore for inline assembly. In general,Chad Rosier
2012-10-29This patch addresses a problem with the Post RA scheduler generating anPreston Gurd
2012-10-26Fix typo in comment.Nick Lewycky
2012-10-15misched: ILP scheduler for experimental heuristics.Andrew Trick
2012-10-10misched: Use the TargetSchedModel interface wherever possible.Andrew Trick
2012-10-09misched: Remove LoopDependencies heuristic.Andrew Trick
2012-10-08misched: remove the unused getSpecialAddressLatency hook.Andrew Trick
2012-10-08misched: remove forceUnitLatencies. Defaults are handled by the default Sched...Andrew Trick
2012-09-18misched: Make ScheduleDAGInstrs use the TargetSchedule interface.Andrew Trick
2012-09-11Release build: guard dump functions withManman Ren
2012-09-06Release build: guard dump functions with "ifndef NDEBUG"Manman Ren
2012-08-29Rename hasVolatileMemoryRef() to hasOrderedMemoryRef().Jakob Stoklund Olesen
2012-08-23Simplify the computeOperandLatency API.Andrew Trick
2012-07-30Use the latest MachineRegisterInfo APIs. No functionality.Andrew Trick
2012-07-28Reenable a basic SSA DAG builder optimization.Andrew Trick
2012-06-14misched: disable SSA check pending PR13112.Andrew Trick
2012-06-13sched: fix latency of memory dependence chain edges for consistency.Andrew Trick
2012-06-06Move RegisterPressure.h.Andrew Trick
2012-06-06Remove unused private fields found by clang's new -Wunused-private-field.Benjamin Kramer
2012-06-05misched: API for minimum vs. expected latency.Andrew Trick
2012-06-01Switch all register list clients to the new MC*Iterator interface.Jakob Stoklund Olesen
2012-05-20Use LiveRangeQuery in ScheduleDAGInstrs.Jakob Stoklund Olesen
2012-05-15Add -enable-aa-sched-mi, off by default, for AliasAnalysis inside MachineSche...Andrew Trick
2012-04-24misched: DAG builder must special case earlyclobberAndrew Trick
2012-04-24misched: DAG builder support for tracking register pressure within the curren...Andrew Trick
2012-04-20New and improved comment.Andrew Trick
2012-04-20SparseSet: Add support for key-derived indexes and arbitrary key types.Andrew Trick
2012-04-20misched: initialize BBAndrew Trick
2012-04-13misched: Added CanHandleTerminators.Andrew Trick
2012-03-16ScheduleDAGInstrs: When adding uses we add them into a set that's empty at th...Benjamin Kramer
2012-03-16misched: add DAG edges from vreg defs to ExitSU.Andrew Trick
2012-03-14misched: implemented a framework for top-down or bottom-up scheduling.Andrew Trick
2012-03-09misched interface: rename Begin/End to RegionBegin/RegionEnd since they are n...Andrew Trick
2012-03-07misched prep: Expose the ScheduleDAGInstrs interface so targets mayAndrew Trick
2012-03-07misched prep: Comment the ScheduleDAGInstrs interface.Andrew Trick
2012-03-07misched prep: Cleanup ScheduleDAGInstrs interface.Andrew Trick
2012-03-07misched prep: rename InsertPos to End.Andrew Trick
2012-03-07misched preparation: rename core scheduler methods for consistency.Andrew Trick
2012-03-07misched preparation: clarify ScheduleDAG and ScheduleDAGInstrs roles.Andrew Trick
2012-03-07misched preparation: modularize schedule emission.Andrew Trick
2012-03-07Cleanup in preparation for misched: Move DAG visualization logic.Andrew Trick
2012-03-04Use uint16_t to store register overlaps to reduce static data.Craig Topper
2012-02-24PostRA sched: speed up physreg tracking by not abusing SparseSet.Andrew Trick
2012-02-23misched: cleanup reaching def computationAndrew Trick
2012-02-23PostRASched: Convert physreg def/use tracking to Jakob's SparseSet.Andrew Trick
2012-02-22Don't compute latencies for regmask operands.Jakob Stoklund Olesen
2012-02-22misched: Use SparseSet for VRegDegs for constant time clear().Andrew Trick
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