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path: root/lib/CodeGen/ScheduleDAGInstrs.cpp
AgeCommit message (Expand)Author
2012-06-14misched: disable SSA check pending PR13112.Andrew Trick
2012-06-13sched: fix latency of memory dependence chain edges for consistency.Andrew Trick
2012-06-06Move RegisterPressure.h.Andrew Trick
2012-06-06Remove unused private fields found by clang's new -Wunused-private-field.Benjamin Kramer
2012-06-05misched: API for minimum vs. expected latency.Andrew Trick
2012-06-01Switch all register list clients to the new MC*Iterator interface.Jakob Stoklund Olesen
2012-05-20Use LiveRangeQuery in ScheduleDAGInstrs.Jakob Stoklund Olesen
2012-05-15Add -enable-aa-sched-mi, off by default, for AliasAnalysis inside MachineSche...Andrew Trick
2012-04-24misched: DAG builder must special case earlyclobberAndrew Trick
2012-04-24misched: DAG builder support for tracking register pressure within the curren...Andrew Trick
2012-04-20New and improved comment.Andrew Trick
2012-04-20SparseSet: Add support for key-derived indexes and arbitrary key types.Andrew Trick
2012-04-20misched: initialize BBAndrew Trick
2012-04-13misched: Added CanHandleTerminators.Andrew Trick
2012-03-16ScheduleDAGInstrs: When adding uses we add them into a set that's empty at th...Benjamin Kramer
2012-03-16misched: add DAG edges from vreg defs to ExitSU.Andrew Trick
2012-03-14misched: implemented a framework for top-down or bottom-up scheduling.Andrew Trick
2012-03-09misched interface: rename Begin/End to RegionBegin/RegionEnd since they are n...Andrew Trick
2012-03-07misched prep: Expose the ScheduleDAGInstrs interface so targets mayAndrew Trick
2012-03-07misched prep: Comment the ScheduleDAGInstrs interface.Andrew Trick
2012-03-07misched prep: Cleanup ScheduleDAGInstrs interface.Andrew Trick
2012-03-07misched prep: rename InsertPos to End.Andrew Trick
2012-03-07misched preparation: rename core scheduler methods for consistency.Andrew Trick
2012-03-07misched preparation: clarify ScheduleDAG and ScheduleDAGInstrs roles.Andrew Trick
2012-03-07misched preparation: modularize schedule emission.Andrew Trick
2012-03-07Cleanup in preparation for misched: Move DAG visualization logic.Andrew Trick
2012-03-04Use uint16_t to store register overlaps to reduce static data.Craig Topper
2012-02-24PostRA sched: speed up physreg tracking by not abusing SparseSet.Andrew Trick
2012-02-23misched: cleanup reaching def computationAndrew Trick
2012-02-23PostRASched: Convert physreg def/use tracking to Jakob's SparseSet.Andrew Trick
2012-02-22Don't compute latencies for regmask operands.Jakob Stoklund Olesen
2012-02-22misched: Use SparseSet for VRegDegs for constant time clear().Andrew Trick
2012-02-22Comment from code reviewAndrew Trick
2012-02-22misched: DAG builder should not track dependencies for SSA defs.Andrew Trick
2012-02-22Initialize SUnits before DAG building.Andrew Trick
2012-02-21Clear virtual registers after they are no longer referenced.Andrew Trick
2012-01-14misched: Initial code for building an MI level scheduling DAGAndrew Trick
2012-01-14Move physreg dependency generation into aptly named addPhysRegDeps.Andrew Trick
2012-01-14misched: Added ScheduleDAGInstrs::IsPostRAAndrew Trick
2012-01-07Added a late machine instruction copy propagation pass. This catchesEvan Cheng
2012-01-05Remove an unused variable.Chandler Carruth
2012-01-05Minor postra scheduler cleanup. It could result in more precise antidependenc...Andrew Trick
2011-12-14Model ARM predicated write as read-mod-write. e.g.Evan Cheng
2011-12-14Allow target to specify register output dependency. Still default to one.Evan Cheng
2011-12-14- Add MachineInstrBundle.h and MachineInstrBundle.cpp. This includes a functionEvan Cheng
2011-12-07Add bundle aware API for querying instruction properties and switch the codeEvan Cheng
2011-12-06First chunk of MachineInstr bundle support.Evan Cheng
2011-12-02make sure ScheduleDAGInstrs::EmitSchedule does not crash when the first instr...Hal Finkel
2011-10-07PostRA scheduler fix. Clear stale loop dependencies.Andrew Trick
2011-10-07whitespaceAndrew Trick