emscripten-fastcomp - LLVM with the emscripten fastcomp javascript backend

Age	Commit message (Expand)	Author
2012-09-11	Reorganize MachineScheduler interfaces and publish them in the header.	Andrew Trick
2012-09-06	Release build: guard dump functions with "ifndef NDEBUG"	Manman Ren
2012-08-23	Simplify the computeOperandLatency API.	Andrew Trick
2012-08-22	Add a getName function to MachineFunction. Use it in places that previously d...	Craig Topper
2012-07-23	Fix a typo (the the => the)	Sylvestre Ledru
2012-07-07	I'm introducing a new machine model to simultaneously allow simple	Andrew Trick
2012-07-02	misched: allow NULL InstrItineraries.	Andrew Trick
2012-06-29	misched: avoid scheduling instructions that can't be dispatched.	Andrew Trick
2012-06-29	misched: count micro-ops toward the issue limit.	Andrew Trick
2012-06-16	Guard private fields that are unused in Release builds with #ifndef NDEBUG.	Benjamin Kramer
2012-06-06	Move RegisterClassInfo.h.	Andrew Trick
2012-06-06	Move RegisterPressure.h.	Andrew Trick
2012-06-05	misched: API for minimum vs. expected latency.	Andrew Trick
2012-06-05	misched: comments from code review.	Andrew Trick
2012-05-25	misched: trace formatting	Andrew Trick
2012-05-24	Silence unused variable warnings from when assertions are disabled.	Kaelyn Uhrain
2012-05-24	misched: Use the same scheduling heuristics with -misched-topdown/bottomup.	Andrew Trick
2012-05-24	misched: Trace regpressure.	Andrew Trick
2012-05-24	misched: Give each ReadyQ a unique ID	Andrew Trick
2012-05-24	misched: Added ScoreboardHazardRecognizer.	Andrew Trick
2012-05-24	misched: Release bottom roots in reverse order.	Andrew Trick
2012-05-24	misched: rename ReadyQ class	Andrew Trick
2012-05-24	misched: copy comments so compareRPDelta is readable by itself.	Andrew Trick
2012-05-17	comments	Andrew Trick
2012-05-17	misched: trace ReadyQ.	Andrew Trick
2012-05-17	misched: Added 3-level regpressure back-off.	Andrew Trick
2012-05-17	comment	Andrew Trick
2012-05-17	misched: fix liveness iterators	Andrew Trick
2012-05-10	misched: Print machineinstrs with -debug-only=misched	Andrew Trick
2012-05-10	misched: tracing register pressure heuristics.	Andrew Trick
2012-05-10	misched: Add register pressure backoff to ConvergingScheduler.	Andrew Trick
2012-05-10	misched: Release only unscheduled nodes into ReadyQ.	Andrew Trick
2012-05-10	misched: Added ReadyQ container wrapper for Top and Bottom Queues.	Andrew Trick
2012-05-10	misched: Introducing Top and Bottom register pressure trackers during schedul...	Andrew Trick
2012-04-24	Fix a naughty header include that breaks "installed" builds.	Andrew Trick
2012-04-24	misched: try (not too hard) to place debug values where they belong	Andrew Trick
2012-04-24	misched: ignore debug values during scheduling	Andrew Trick
2012-04-24	misched: DAG builder support for tracking register pressure within the curren...	Andrew Trick
2012-04-01	misched: Add finalizeScheduler to complete the target interface.	Andrew Trick
2012-03-21	misched: trace LiveIntervals after scheduling.	Andrew Trick
2012-03-21	misched: obvious iterator update fixes for bottom-up.	Andrew Trick
2012-03-21	misched: cleanup main loop	Andrew Trick
2012-03-19	Add an option to the MI scheduler to cut off scheduling after a fixed number of	Lang Hames
2012-03-14	Silence operator precedence warnings.	Benjamin Kramer
2012-03-14	misched: implemented a framework for top-down or bottom-up scheduling.	Andrew Trick
2012-03-14	misched comments	Andrew Trick
2012-03-09	misched: handle scheduler that insert instructions at empty region boundaries.	Andrew Trick
2012-03-09	misched: handle scheduling region boundaries nicely.	Andrew Trick
2012-03-09	misched interface: rename Begin/End to RegionBegin/RegionEnd since they are n...	Andrew Trick
2012-03-09	misched comments	Andrew Trick