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and those derived from them. These are obnoxious because
they were written as: PatLeaf<(bitconvert). Not having an
argument was foiling adding better type checking for operand
count matching up with what was required (in this case,
bitconvert always requires an operand!)
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needed here.
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beyond just calling getTypeToTransformTo.
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particular instruction + fixups might need relaxation.
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dependencies in MCMachOStreamer and MCAssembler.
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implementation.
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- MCAssembler is now object-file independent, although we will surely need more work to fully support ELF/COFF.
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specific not object writer specific task.
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dag isel gen instead of instruction properties. This
allows the oh-so-useful behavior of matching a variadic
non-root node.
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to allow custom post-processing of matched instructions.
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symbol differences, basically whether the assembler should attempt to understand atoms when using scattered symbols.
Also, avoid some virtual call overhead.
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external relocations, but we don't have x86_64 relocations yet).
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and passing off ownership to AsmPrinter. Now MachineModuleInfo
creates it and owns it by value. This allows us to use MCSymbols
more consistently throughout the rest of the code generator, and
simplifies a bit of code. This also allows MachineFunction to
keep an MCContext reference handy, and cleans up the TargetRegistry
interfaces for AsmPrinters.
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for a global instead of messing around with string buffers.
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No functionality change.
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just make unnamed temp symbols instead of having to come
up with its own names.
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where we used ot create an MCSymbol for ".". Now emit an assembler
temporary label and reference it instead of "." textually.
rdar://7739457
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an MCExpr and not an MCSymbol. Change it to take an MCStreamer,
which is currently unused.
No functionality change.
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semantic instead of syntactic. This completes MCization of
darwin/x86[-64]!
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is preparatory to having PEI's scavenged frame index value reuse logic
properly distinguish types of frame values (e.g., whether the value is
stack-pointer relative or frame-pointer relative).
No functionality change.
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whether it should skip checking defs or at least virtual register defs. This subsumes part of the TargetInstrInfo::isIdentical functionality.
- Eliminate TargetInstrInfo::isIdentical and replace it with produceSameValue. In the default case, produceSameValue just checks whether two machine instructions are identical (except for virtual register defs). But targets may override it to check for unusual cases (e.g. ARM pic loads from constant pools).
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after LSR, so that clients can opt in.
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terms of store and load, which means bitcasting between scalar
integer and vector has endian-specific results, which undermines
this whole approach.
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the number of value bits, not the number of bits of allocation for in-memory
storage.
Make getTypeStoreSize and getTypeAllocSize work consistently for arrays and
vectors.
Fix several places in CodeGen which compute offsets into in-memory vectors
to use TargetData information.
This fixes PR1784.
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126.gcc nightly tests. These failures uncovered latent bugs that machine DCE
could remove one half of a stack adjust down/up pair, causing PEI to assert.
This update fixes that, and the tests now pass.
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