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2010-05-11The getDefaultSubtargetFeatures method of SubtargetFeature did actually return aBill Wendling
string of features for that target. However LTO was using that string to pass into the "create target machine" stuff. That stuff needed the feature string to be in a particular form. In particular, it needed the CPU specified first and then the attributes. If there isn't a CPU specified, it required it to be blank -- e.g., ",+altivec". Yuck. Modify the getDefaultSubtargetFeatures method to be a non-static member function. For all attributes for a specific subtarget, it will add them in like normal. It will also take a CPU string so that it can satisfy this horrible syntax. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103451 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that itDan Gohman
doesn't have to guess. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103194 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103193 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-04MC/Matcher: Add support for over-riding the default MatchInstruction functionDaniel Dunbar
name (for example, to allow targets to interpose the actual MatchInstruction function). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102987 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-02Remove the -enable-sjlj-eh option, which doesn't do anything.Duncan Sands
Remove the -enable-eh option which is only used by the JIT, and replace it with -jit-enable-eh. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102865 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-01Add a pseudo instruction REG_SEQUENCE that takes a list of registers andEvan Cheng
sub-register indices and outputs a single super register which is formed from a consecutive sequence of registers. This is used as register allocation / coalescing aid and it is useful to represent instructions that output register pairs / quads. For example, v1024, v1025 = vload <address> where v1024 and v1025 forms a register pair. This really should be modelled as v1024<3>, v1025<4> = vload <address> but it would violate SSA property before register allocation is done. Currently we use insert_subreg to form the super register: v1026 = implicit_def v1027 - insert_subreg v1026, v1024, 3 v1028 = insert_subreg v1027, v1025, 4 ... = use v1024 = use v1028 But this adds pseudo live interval overlap between v1024 and v1025. We can now modeled it as v1024, v1025 = vload <address> v1026 = REG_SEQUENCE v1024, 3, v1025, 4 ... = use v1024 = use v1026 After coalescing, it will be v1026<3>, v1025<4> = vload <address> ... = use v1026<3> = use v1026 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102815 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-01Get rid of the EdgeMapping map. Instead, just check for BasicBlockDan Gohman
changes before doing phi lowering for switches. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102809 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-29Frame index can be negative.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102577 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-26on darwin empty functions need to codegen into something of non-zero length,Chris Lattner
otherwise labels get incorrectly merged. We handled this by emitting a ".byte 0", but this isn't correct on thumb/arm targets where the text segment needs to be a multiple of 2/4 bytes. Handle this by emitting a noop. This is more gross than it should be because arm/ppc are not fully mc'ized yet. This fixes rdar://7908505 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102400 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-26Add PPC AsmPrinter handling for target-specific form ofDale Johannesen
DBG_VALUE, and a cautionary comment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102371 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-26- Move TargetLowering::EmitTargetCodeForFrameDebugValue to TargetInstrInfo ↵Evan Cheng
and rename it to emitFrameIndexDebugValue. - Teach spiller to modify DBG_VALUE instructions to reference spill slots. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102323 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-25Stop abusing EmitInstrWithCustomInserter for target-dependentDale Johannesen
form of DEBUG_VALUE, as it doesn't have reasonable default behavior for unsupported targets. Add a new hook instead. No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102320 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-22Move HandlePHINodesInSuccessorBlocks functions out of SelectionDAGISelDan Gohman
and into SelectionDAGBuilder and FastISel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102123 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-21Implement -disable-non-leaf-fp-elim which disable frame pointer eliminationEvan Cheng
optimization for non-leaf functions. This will be hooked up to gcc's -momit-leaf-frame-pointer option. rdar://7886181 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101984 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-21Add more const qualifiers on TargetMachine and friends.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101977 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-20Because of the EMMS problem, right now we have to supportDale Johannesen
user-defined operations that use MMX register types, but the compiler shouldn't generate them on its own. This adds a Synthesizable abstraction to represent this, and changes the vector widening computation so it won't produce MMX types. (The motivation is to remove noise from the ABI compatibility part of the gcc test suite, which has some breakage right now.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101951 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-20Document that TargetRegisterInfo::contains does not cover virtual registers.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101903 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-18Make processor FUs unique for given itinerary. This extends the limit of 32Anton Korobeynikov
FU per CPU arch to 32 per intinerary allowing precise modelling of quite complex pipelines in the future. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101754 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17Use const qualifiers with TargetLowering. This eliminates severalDan Gohman
const_casts, and it reinforces the design of the Target classes being immutable. SelectionDAGISel::IsLegalToFold is now a static member function, because PIC16 uses it in an unconventional way. There is more room for API cleanup here. And PIC16's AsmPrinter no longer uses TargetLowering. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101635 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17More work to allow dag combiner to promote 16-bit ops to 32-bit.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101621 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-16Add a getSelectionDAGInfo member to TargetMachine.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101567 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-16Create a new TargetSelectionDAGInfo class. This will eventually acquireDan Gohman
SelectionDAG-specific parts of TargetLowering. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101537 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-16Eliminate an unnecessary SelectionDAG dependency in getOptimalMemOpType.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101531 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-16Fix this code to avoid implicit assumptions about the length of the array.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101530 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-16Adding support for dag combiner to promote operations for profit. This ↵Evan Cheng
requires target specific queries. For example, x86 should promote i16 to i32 when it does not impact load folding. x86 support is off by default. It can be enabled with -promote-16bit. Work in progress. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101448 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-15Add const qualifiers to CodeGen's use of LLVM IR constructs.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101334 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-14Factor out EH landing pad code into a separate function, and constifyDan Gohman
a bunch of stuff to support it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101273 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-13add llvm codegen support for -ffunction-sections and -fdata-sections,Chris Lattner
patch by Sylvere Teissier! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101106 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-08Avoid using f64 to lower memcpy from constant string. It's cheaper to use ↵Evan Cheng
i32 store of immediates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100751 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07Fix typo.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100726 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07Remove late ARM codegen optimization pass committed by accident.Anton Korobeynikov
It is not ready for public yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100673 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07Since tblgen bug was fixed (thanks Jakob!) we don't need InstrStage2 hack ↵Anton Korobeynikov
anymore. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100667 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07Make use of new reserved/required scheduling stuff: introduce VFP and NEON ↵Anton Korobeynikov
locks to model domain cross stalls precisly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100646 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07Initial support for different kinds of FU reservation.Anton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100645 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07Add hook to insert late LLVM=>LLVM passes just before iselAnton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100640 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-05unthread MMI from FastISelChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100416 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-05trim some spurious references to DwarfWriter. SDIsel really doesn'tChris Lattner
need it anymore, so don't addRequire it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100400 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-05Replace TSFlagsFields and TSFlagsShifts with a simpler TSFlags field.Jakob Stoklund Olesen
When a target instruction wants to set target-specific flags, it should simply set bits in the TSFlags bit vector defined in the Instruction TableGen class. This works well because TableGen resolves member references late: class I : Instruction { AddrMode AM = AddrModeNone; let TSFlags{3-0} = AM.Value; } let AM = AddrMode4 in def ADD : I; TSFlags gets the expected bits from AddrMode4 in this example. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100384 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-05fastisel doesn't need DwarfWriter, remove some tendricles.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100381 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-04Momentous day: remove the "O" member from AsmPrinter. Now all Chris Lattner
"asm printering" happens through MCStreamer. This also Streamerizes PIC16 debug info, which escaped my attention. This removes a leak from LLVMTargetMachine of the 'legacy' output stream. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100327 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-04fix an ugly wart in the MCInstPrinter api where theChris Lattner
raw_ostream to print an instruction to had to be specified at MCInstPrinter construction time instead of being able to pick at each call to printInstruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100307 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-04Reapply address space patch after fixing an issue in MemCopyOptimizer.Mon P Wang
Added support for address spaces and added a isVolatile field to memcpy, memmove, and memset, e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100304 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-02Correctly lower memset / memcpy of undef. It should be a nop. PR6767.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100208 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-02Revert r100191 since it breaks objc in clang Mon P Wang
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100199 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-02Reapply address space patch after fixing an issue in MemCopyOptimizer.Mon P Wang
Added support for address spaces and added a isVolatile field to memcpy, memmove, and memset, e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100191 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-01Add comments about DstAlign and SrcAlign.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100132 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-01- Avoid using floating point stores to implement memset unless the value is ↵Evan Cheng
zero. - Do not try to infer GV alignment unless its type is sized. It's not possible to infer alignment if it has opaque type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100118 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-01Fix sdisel memcpy, memset, memmove lowering:Evan Cheng
1. Makes it possible to lower with floating point loads and stores. 2. Avoid unaligned loads / stores unless it's fast. 3. Fix some memcpy lowering logic bug related to when to optimize a load from constant string into a constant. 4. Adjust x86 memcpy lowering threshold to make it more sane. 5. Fix x86 target hook so it uses vector and floating point memory ops more effectively. rdar://7774704 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100090 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-30Revert Mon Ping's change 99928, since it broke all the llvm-gcc buildbots.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99948 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-30Added support for address spaces and added a isVolatile field to memcpy, ↵Mon P Wang
memmove, and memset, e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1) A update of langref will occur in a subsequent checkin. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99928 91177308-0d34-0410-b5e6-96231b3b80d8
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