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2010-07-21Teach bottom up pre-ra scheduler to track register pressure. Work in progress.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108991 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-20Grammar.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108814 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-20Constify some arguments.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108812 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-19ARM has to provide its own TargetLowering::findRepresentativeClass because ↵Evan Cheng
its scalar floating point registers alias its vector registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108761 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-19Teach computeRegisterProperties() to compute "representative" register class ↵Evan Cheng
for legal value types. A "representative" register class is the largest legal super-reg register class for a value type. e.g. On i386, GR32 is the rep register class for i8 / i16 / i32; on x86_64 it would be GR64. This property will be used by the register pressure tracking instruction scheduler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108735 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-19TblGen/AsmMatcher: Add support for honoring instruction Requires<[]> ↵Daniel Dunbar
attributes as part of the matcher. - Currently includes a hack to limit ourselves to "In32BitMode" and "In64BitMode", because we don't have the other infrastructure to properly deal with setting SSE, etc. features on X86. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108677 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-19Target: Give the TargetAsmParser access to the TargetMachine.Daniel Dunbar
- Unfortunate, but necessary for now to handle subtarget instruction matching. Eventually we should factor out the lower level target machine information so we don't need to do this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108664 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-16Remove the isMoveInstr() hook.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108567 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-16Rename DBG_LABEL PROLOG_LABEL, because it's only used during prolog emission andBill Wendling
thus is a much more meaningful name. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108563 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-16Remove remaining calls to TII::isMoveInstr.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108556 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-15Split -enable-finite-only-fp-math to two options:Evan Cheng
-enable-no-nans-fp-math and -enable-no-infs-fp-math. All of the current codegen fp math optimizations only care whether the fp arithmetics arguments and results can never be NaN. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108465 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-1580-col.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108420 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-14Don't pass StringRef by reference.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108366 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-13Update comment.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108272 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-12Fix a typo and fit in 80 columns. Found by Bob Wilson.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108164 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-12MC: Add MCAsmParserExtension, a base class for all the target/object specificDaniel Dunbar
classes which want to extend the basic asm parser. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108158 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-12Convert the last use of getPhysicalRegisterRegClass and remove it.Rafael Espindola
AggressiveAntiDepBreaker should not be using getPhysicalRegisterRegClass. An instruction might be using a register that can only be replaced with one from a subclass of getPhysicalRegisterRegClass. With this patch we use getMinimalPhysRegClass. This is correct, but conservative. We should check the uses of the register and select the largest register class that can be used in all of them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108122 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-11Remove TargetInstrInfo::copyRegToReg entirely.Jakob Stoklund Olesen
Targets must now implement TargetInstrInfo::copyPhysReg instead. There is no longer a default implementation forwarding to copyRegToReg. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108095 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-11Make getPhysicalRegisterRegClass non-virtual. Should be able to remove it soon.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108094 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-11Remove copyRegToReg from TargetInstrInfo so it is not longer accesible.Jakob Stoklund Olesen
Use a COPY instruction instead for register copies, or TII::copyPhysReg() after COPY instructions are lowered. Targets should implement copyPhysReg instead of copyRegToReg. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108075 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-11Fix va_arg for doubles. With this patch VAARG nodes always contain theRafael Espindola
correct alignment information, which simplifies ExpandRes_VAARG a bit. The patch introduces a new alignment information to TargetLoweringInfo. This is needed since the two natural candidates cannot be used: * The 's' in target data: If this is set to the minimal alignment of any argument, getCallFrameTypeAlignment would return 4 for doubles on ARM for example. * The getTransientStackAlignment method. It is possible for an architecture to have argument less aligned than what we maintain the stack pointer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108072 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-10Reapply bottom-up fast-isel, with several fixes for x86-32:Dan Gohman
- Check getBytesToPopOnReturn(). - Eschew ST0 and ST1 for return values. - Fix the PIC base register initialization so that it doesn't ever fail to end up the top of the entry block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108039 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09Automatically fold COPY instructions into stack load/store.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108012 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09Change TII::foldMemoryOperand API to require the machine instruction to beJakob Stoklund Olesen
inserted in a MBB, and return an already inserted MI. This target API change is necessary to allow foldMemoryOperand to call storeToStackSlot and loadFromStackSlot when folding a COPY to a stack slot reference in a target independent way. The foldMemoryOperandImpl hook is going to change in the same way, but I'll wait until COPY folding is actually implemented. Most targets only fold copies and won't need to specialize this hook at all. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107991 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09--- Reverse-merging r107947 into '.':Bob Wilson
U utils/TableGen/FastISelEmitter.cpp --- Reverse-merging r107943 into '.': U test/CodeGen/X86/fast-isel.ll U test/CodeGen/X86/fast-isel-loads.ll U include/llvm/Target/TargetLowering.h U include/llvm/Support/PassNameParser.h U include/llvm/CodeGen/FunctionLoweringInfo.h U include/llvm/CodeGen/CallingConvLower.h U include/llvm/CodeGen/FastISel.h U include/llvm/CodeGen/SelectionDAGISel.h U lib/CodeGen/LLVMTargetMachine.cpp U lib/CodeGen/CallingConvLower.cpp U lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp U lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp U lib/CodeGen/SelectionDAG/FastISel.cpp U lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp U lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp U lib/CodeGen/SelectionDAG/InstrEmitter.cpp U lib/CodeGen/SelectionDAG/TargetLowering.cpp U lib/Target/XCore/XCoreISelLowering.cpp U lib/Target/XCore/XCoreISelLowering.h U lib/Target/X86/X86ISelLowering.cpp U lib/Target/X86/X86FastISel.cpp U lib/Target/X86/X86ISelLowering.h git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107987 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09Re-apply bottom-up fast-isel, with fixes. Be very careful to avoid emittingDan Gohman
a DBG_VALUE after a terminator, or emitting any instructions before an EH_LABEL. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107943 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08Implement X86InstrInfo::copyPhysRegJakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107898 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08Convert EXTRACT_SUBREG to COPY when emitting machine instrs.Jakob Stoklund Olesen
EXTRACT_SUBREG no longer appears as a machine instruction. Use COPY instead. Add isCopy() checks in many places using isMoveInstr() and isExtractSubreg(). The isMoveInstr hook will be removed later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107879 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08Add TargetInstrInfo::copyPhysReg hook and use it from LowerSubregs.Jakob Stoklund Olesen
This target hook is intended to replace copyRegToReg entirely, but for now it calls copyRegToReg. Any remaining calls to copyRegToReg wil be replaced by COPY instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107854 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08Revert 107840 107839 107813 107804 107800 107797 107791.Dan Gohman
Debug info intrinsics win for now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107850 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07Add X86FastISel support for return statements. This entails refactoringDan Gohman
a bunch of stuff, to allow the target-independent calling convention logic to be employed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107800 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07Simplify FastISel's constructor by giving it a FunctionLoweringInfoDan Gohman
instance, rather than pointers to all of FunctionLoweringInfo's members. This eliminates an NDEBUG ABI sensitivity. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107789 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07Split the SDValue out of OutputArg so that SelectionDAG-independentDan Gohman
code can do calling-convention queries. This obviates OutputArgReg. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107786 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07Move ArgFlagsTy, OutputArg, and InputArg out of SelectionDAGNodes.h andDan Gohman
into a new header, TargetCallingConv.h. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107782 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-06CanLowerReturn doesn't need a SelectionDAG; it just needs an LLVMContext.Dan Gohman
SelectBasicBlock doesn't needs its BasicBlock argument. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107712 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-06Make getMinimalPhysRegClass' comment mention what makes it differentDan Gohman
from getPhysicalRegisterRegClass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107660 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-06Fix up -fstack-protector on linux to use the segmentEric Christopher
registers. Split out testcases per architecture and os now. Patch from Nelson Elhage. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107640 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-02Add a new target independent COPY instruction and code to lower it.Jakob Stoklund Olesen
The COPY instruction is intended to replace the target specific copy instructions for virtual registers as well as the EXTRACT_SUBREG and INSERT_SUBREG instructions in MachineFunctions. It won't we used in a selection DAG. COPY is lowered to native register copies by LowerSubregs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107529 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-02Clean up TargetOpcodes.h a bit, and limit the number of places where the fullJakob Stoklund Olesen
list of predefined instructions appear. Add some consistency checks. Ideally, TargetOpcodes.h should be produced by TableGen from Target.td, but it is hardly worth the effort. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107520 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29Revert r107205 and r107207.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107215 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29Introducing the "linker_weak" linkage type. This will be used for Objective-CBill Wendling
metadata types which should be marked as "weak", but which the linker will remove upon final linkage. For example, the "objc_msgSend_fixup_alloc" symbol is defined like this: .globl l_objc_msgSend_fixup_alloc .weak_definition l_objc_msgSend_fixup_alloc .section __DATA, __objc_msgrefs, coalesced .align 3 l_objc_msgSend_fixup_alloc: .quad _objc_msgSend_fixup .quad L_OBJC_METH_VAR_NAME_1 This is different from the "linker_private" linkage type, because it can't have the metadata defined with ".weak_definition". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107205 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29Add a VT argument to getMinimalPhysRegClass and replace the copy related usesRafael Espindola
of getPhysicalRegisterRegClass with it. If we want to make a copy (or estimate its cost), it is better to use the smallest class as more efficient operations might be possible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107140 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25Change if-conversion block size limit checks to add some flexibility.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106901 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25The hasMemory argument is irrelevant to how the argumentDale Johannesen
for an "i" constraint should get lowered; PR 6309. While this argument was passed around a lot, this is the only place it was used, so it goes away from a lot of other places. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106893 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24Edit and clarify comments for TargetInstrInfo methods:Bob Wilson
None of the existing implementations of commuteInstruction create new instructions unless the NewMI parameter is true, but the comment had implied otherwise. findCommutedOpIndices returns false, not true, when it doesn't know how to commute the instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106761 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24Reapply r106634, now that the bug it exposed is fixed.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106746 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-23Revert r106263, "Fold the ShrinkDemandedOps pass into the regular ↵Daniel Dunbar
DAGCombiner pass,"... it was causing both 'file' (with clang) and 176.gcc (with llvm-gcc) to be miscompiled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106634 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-23Some targets don't require the fencing MEMBARRIER instructions surroundingJim Grosbach
atomic intrinsics, either because the use locking instructions for the atomics, or because they perform the locking directly. Add support in the DAG combiner to fold away the fences. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106630 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-23remove trailing whitespaceJim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106628 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-22Tail merging pass shall not break up IT blocks. rdar://8115404Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106517 91177308-0d34-0410-b5e6-96231b3b80d8
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