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2010-09-10add a comment explicitly calling out that allocation orders may includeJim Grosbach
reserved regs and that register allocators need to explicitly check for them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113593 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-10Teach if-converter to be more careful with predicating instructions that wouldEvan Cheng
take multiple cycles to decode. For the current if-converter clients (actually only ARM), the instructions that are predicated on false are not nops. They would still take machine cycles to decode. Micro-coded instructions such as LDM / STM can potentially take multiple cycles to decode. If-converter should take treat them as non-micro-coded simple instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113570 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-09For each instruction itinerary class, specify the number of micro-ops eachEvan Cheng
instruction in the class would be decoded to. Or zero if the number of uOPs must be determined dynamically. This will be used to determine the cost-effectiveness of predicating a micro-coded instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113513 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-03Reapply this increase to the number of virtual registers. All of theEric Christopher
various breakages appear to be dealt with. Patch by Pekka Jääskeläinen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113024 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-30Fix LLVM target initialization to deal with sociopathic outside projectsEric Christopher
that like to randomly define things like "X86", regenerate autoconf bits and update cmake. Fixes PR7852. Patch by Xerxes Rånby! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112499 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-27Fix a couple of typos.Eric Christopher
Patch by Cameron Esfahani! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112297 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-26Simplify eliminateFrameIndex() interface back down now that PEI doesn't needJim Grosbach
to try to re-use scavenged frame index reference registers. rdar://8277890 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112241 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-26tidy up a bit. no functional change.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112228 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-25add a specialization for the MVT form of getTypeAction, since it isChris Lattner
trivial. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112105 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-25remove some llvmcontext arguments that are now dead post-refactoring.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112104 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-25Change handling of illegal vector types to widen when possible instead of Chris Lattner
expanding: e.g. <2 x float> -> <4 x float> instead of -> 2 floats. This affects two places in the code: handling cross block values and handling function return and arguments. Since vectors are already widened by legalizetypes, this gives us much better code and unblocks x86-64 abi and SPU abi work. For example, this (which is a silly example of a cross-block value): define <4 x float> @test2(<4 x float> %A) nounwind { %B = shufflevector <4 x float> %A, <4 x float> undef, <2 x i32> <i32 0, i32 1> %C = fadd <2 x float> %B, %B br label %BB BB: %D = fadd <2 x float> %C, %C %E = shufflevector <2 x float> %D, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> ret <4 x float> %E } Now compiles into: _test2: ## @test2 ## BB#0: addps %xmm0, %xmm0 addps %xmm0, %xmm0 ret previously it compiled into: _test2: ## @test2 ## BB#0: addps %xmm0, %xmm0 pshufd $1, %xmm0, %xmm1 ## kill: XMM0<def> XMM0<kill> XMM0<def> insertps $0, %xmm0, %xmm0 insertps $16, %xmm1, %xmm0 addps %xmm0, %xmm0 ret This implements rdar://8230384 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112101 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-24Add ARM heuristic for when to allocate a virtual base register for stackJim Grosbach
access. rdar://8277890&7352504 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111968 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-24Move enabling the local stack allocation pass into the target where it belongs.Jim Grosbach
For now it's still a command line option, but the interface to the generic code doesn't need to know that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111942 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-19Better handling of offsets on frame index references. rdar://8277890Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111585 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-19Re-re-revert this patch. It seems to be causing performanceEric Christopher
and correctness regressions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111527 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-19Reapply the virtual register patch from 109102. The places where we wereEric Christopher
depending on the number of virtual registers appear to have all been handled now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111499 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-18Add hook for re-using virtual base registers for local stack slot access.Jim Grosbach
Nothing fancy, just ask the target if any currently available base reg is in range for the instruction under consideration and use the first one that is. Placeholder ARM implementation simply returns false for now. ongoing saga of rdar://8277890 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111374 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-17Add materialization of virtual base registers for frame indices allocated intoJim Grosbach
the local block. Resolve references to those indices to a new base register. For simplification and testing purposes, a new virtual base register is allocated for each frame index being resolved. The result is truly horrible, but correct, code that's good for exercising the new code paths. Next up is adding thumb1 support, which should be very simple. Following that will be adding base register re-use and implementing a reasonable ARM heuristic for when a virtual base register should be generated at all. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111315 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-17Add hook to examine an instruction referencing a frame index to determineJim Grosbach
whether to allocate a virtual frame base register to resolve the frame index reference in it. Implement a simple version for ARM to aid debugging. In LocalStackSlotAllocation, scan the function for frame index references to local frame indices and ask the target whether to allocate virtual frame base registers for any it encounters. Purely infrastructural for debug output. Next step is to actually allocate base registers, then add intelligent re-use of them. rdar://8277890 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111262 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-12MC/AsmParser: Push the burdon of emitting diagnostics about unmatchedDaniel Dunbar
instructions onto the target specific parser, which can do a better job. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110889 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-12tblgen/AsmMatcher: Always emit the match function as 'MatchInstructionImpl',Daniel Dunbar
target specific parsers can adapt the TargetAsmParser to this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110888 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11Don't use unsigned char for alignments in TargetData. There aren'tDan Gohman
that many of these things, so the memory savings isn't significant, and there are now situations where there can be alignments greater than 128. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110836 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-10Implement register class inflation.Jakob Stoklund Olesen
When splitting a live range, the new registers have fewer uses and the permissible register class may be less constrained. Recompute the register class constraint from the uses of new registers created for a split. This may let them be allocated from a larger set, possibly avoiding a spill. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110703 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-08Use the "isCompare" machine instruction attribute instead of calling theBill Wendling
relatively expensive comparison analyzer on each instruction. Also rename the comparison analyzer method to something more in line with what it actually does. This pass is will eventually be folded into the Machine CSE pass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110539 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-08Fix PR7809 by creating a header for just llvm variables that can beEric Christopher
included in exported interfaces. Update a couple of exported interfaces. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110532 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-08Add back in r109901, which adds a Compare flag to the target instructions. It'sBill Wendling
useful after all. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110531 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-06Reapply r110396, with fixes to appease the Linux buildbot gods.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110460 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-06spellingJim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110457 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-06Fix eabi calling convention when a 64 bit value shadows r3.Rafael Espindola
Without this what was happening was: * R3 is not marked as "used" * ARM backend thinks it has to save it to the stack because of vaarg * Offset computation correctly ignores it * Offsets are wrong git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110446 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-06Revert r109901. The implementation of <rdar://problem/7405933> (r110423) doesn'tBill Wendling
need the Compare flag after all. --- Reverse-merging r109901 into '.': U include/llvm/Target/TargetInstrDesc.h U include/llvm/Target/Target.td U utils/TableGen/InstrInfoEmitter.cpp U utils/TableGen/CodeGenInstruction.cpp U utils/TableGen/CodeGenInstruction.h git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110424 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-06Add the Optimize Compares pass (disabled by default).Bill Wendling
This pass tries to remove comparison instructions when possible. For instance, if you have this code: sub r1, 1 cmp r1, 0 bz L1 and "sub" either sets the same flag as the "cmp" instruction or could be converted to set the same flag, then we can eliminate the "cmp" instruction all together. This is a important for ARM where the ALU instructions could set the CPSR flag, but need a special suffix ('s') to do so. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110423 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-06Revert r110396 to fix buildbots.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110410 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-05Don't use PassInfo* as a type identifier for passes. Instead, use the ↵Owen Anderson
address of the static ID member as the sole unique type identifier. Clean up APIs related to this change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110396 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-05Revert my last commit, apparently it's a runtime issue.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110387 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-05Remove unnecessary include.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110385 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-03build: Add LLVM_NATIVE_ARCHNAME, which has the sensible value, without "Target"Daniel Dunbar
appended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110109 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-01Targets: Add InitializeNativeTargetAsmPrinter(), patch by Jan Sjodin, althoughDaniel Dunbar
rewritten by me to not require updating all the target initialization routine names. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109996 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30Add a "Compare" flag to the target instruction descriptor. This will be usedBill Wendling
later to identify and possibly remove superfluous compare instructions -- those that are testing for and setting a status flag that should already be set. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109901 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-29Grammar.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109775 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-29Plug the remaining MC leaks by giving MCObjectStreamer/MCAsmStreamer ↵Benjamin Kramer
ownership of the TargetAsmBackend and the MCCodeEmitter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109767 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-24Hook in GlobalMerge passAnton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109359 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-24Add hook to insert late LLVM=>LLVM passes just before iselAnton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109354 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-24Add an ILP scheduler. This is a register pressure aware scheduler that'sEvan Cheng
appropriate for targets without detailed instruction iterineries. The scheduler schedules for increased instruction level parallelism in low register pressure situation; it schedules to reduce register pressure when the register pressure becomes high. On x86_64, this is a win for all tests in CFP2000. It also sped up 256.bzip2 by 16%. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109300 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-23- Allow target to specify when is register pressure "too high". In most cases,Evan Cheng
it's too late to start backing off aggressive latency scheduling when most of the registers are in use so the threshold should be a bit tighter. - Correctly handle live out's and extract_subreg etc. - Enable register pressure aware scheduling by default for hybrid scheduler. For ARM, this is almost always a win on # of instructions. It's runtime neutral for most of the tests. But for some kernels with high register pressure it can be a huge win. e.g. 464.h264ref reduced number of spills by 54 and sped up by 20%. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109279 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-23Revert r109102 for now as it's causing JIT miscompilations.Eric Christopher
I'll try to track down why a bit later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109223 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-22Warnings patrol.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109174 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-22eliminate the TargetInstrInfo::GetInstSizeInBytes hook. Chris Lattner
ARM/PPC/MSP430-specific code (which are the only targets that implement the hook) can directly reference their target-specific instrinfo classes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109171 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-22remove the JIT "NeedsExactSize" feature and supporting logic.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109167 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-22Increase the max physreg size. Patch by Pekka Jääskeläinen.Duncan Sands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109102 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-22Initial modifications to MCAssembler and TargetMachine for the MCJIT.Reid Kleckner
Patch by Olivier Meurant! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109080 91177308-0d34-0410-b5e6-96231b3b80d8
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