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2011-01-25[AVX] Add TableGen classes for vector/subvector type constraints.David Greene
This will be used to check patterns referencing a forthcoming INSERT_SUBVECTOR SDNode and will also be used to check EXTRACT_SUBVECTOR nodes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124191 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-23Add support for the --noexecstack option.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124077 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-23Delay the creation of eh_frame so that the user can change the defaults.Rafael Espindola
Add support for SHT_X86_64_UNWIND. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124059 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-21Convert -enable-sched-cycles and -enable-sched-hazard to -disableAndrew Trick
flags. They are still not enable in this revision. Added TargetInstrInfo::isZeroCost() to fix a fundamental problem with the scheduler's model of operand latency in the selection DAG. Generalized unit tests to work with sched-cycles. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123969 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-20Sorry, several patches in one.Evan Cheng
TargetInstrInfo: Change produceSameValue() to take MachineRegisterInfo as an optional argument. When in SSA form, targets can use it to make more aggressive equality analysis. Machine LICM: 1. Eliminate isLoadFromConstantMemory, use MI.isInvariantLoad instead. 2. Fix a bug which prevent CSE of instructions which are not re-materializable. 3. Use improved form of produceSameValue. ARM: 1. Teach ARM produceSameValue to look pass some PIC labels. 2. Look for operands from different loads of different constant pool entries which have same values. 3. Re-implement PIC GA materialization using movw + movt. Combine the pair with a "add pc" or "ldr [pc]" to form pseudo instructions. This makes it possible to re-materialize the instruction, allow machine LICM to hoist the set of instructions out of the loop and make it possible to CSE them. It's a bit hacky, but it significantly improve code quality. 4. Some minor bug fixes as well. With the fixes, using movw + movt to materialize GAs significantly outperform the load from constantpool method. 186.crafty and 255.vortex improved > 20%, 254.gap and 176.gcc ~10%. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123905 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-15fix typoChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123519 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-10Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs ↵Anton Korobeynikov
and fixes here and there. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123170 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-09Remove TargetRegisterInfo::NoRegister.Jakob Stoklund Olesen
Fix the TargetRegisterInfo::NoRegister places where someone preferred typing 'TargetRegisterInfo::NoRegister' instead of typing '0'. Note that TableGen is already emitting xx::NoRegister in xxGenRegisterNames.inc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123140 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-09Change virtual register numbering to make more space for physical registers.Jakob Stoklund Olesen
The numbering plan is now: 0 NoRegister. [1;2^30) Physical registers. [2^30;2^31) Stack slots. [2^31;2^32) Virtual registers. (With -1u and -2u used by DenseMapInfo.) Each segment is filled from the left, so any mistaken interpretation should quickly cause crashes. FirstVirtualRegister has been removed. TargetRegisterInfo provides predicates conversion functions that should be used instead of interpreting register numbers manually. It is now legal to pass NoRegister to isPhysicalRegister() and isVirtualRegister(). The result is false in both cases. It is quite rare to represent stack slots in this way, so isPhysicalRegister() and isVirtualRegister() require that isStackSlot() be checked first if it can possibly return true. This allows a very fast implementation of the common predicates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123137 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-09Teach TargetRegisterInfo how to cram stack slot indexes in with the virtual andJakob Stoklund Olesen
physical register numbers. This makes the hack used in LiveInterval official, and lets LiveInterval be oblivious of stack slots. The isPhysicalRegister() and isVirtualRegister() predicates don't know about this, so when a variable may contain a stack slot, isStackSlot() should always be tested first. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123128 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-09Fix comment.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123125 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-09Replace TargetRegisterInfo::printReg with a PrintReg class that also works ↵Jakob Stoklund Olesen
without a TRI instance. Print virtual registers numbered from 0 instead of the arbitrary FirstVirtualRegister. The first virtual register is printed as %vreg0. TRI::NoRegister is printed as %noreg. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123107 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-08Fix VirtRegMap to use TRI::index2VirtReg and TRI::virtReg2Index instead ofJakob Stoklund Olesen
depending on TRI::FirstVirtualRegister. Also use TRI::printReg instead of printing virtual registers directly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123101 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-08Use an IndexedMap for LiveVariables::VirtRegInfo.Jakob Stoklund Olesen
Provide MRI::getNumVirtRegs() and TRI::index2VirtReg() functions to allow iteration over virtual registers without depending on the representation of virtual register numbers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123098 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-07Do not model all INLINEASM instructions as having unmodelled side effects.Evan Cheng
Instead encode llvm IR level property "HasSideEffects" in an operand (shared with IsAlignStack). Added MachineInstrs::hasUnmodeledSideEffects() to check the operand when the instruction is an INLINEASM. This allows memory instructions to be moved around INLINEASM instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123044 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-07DBG_VALUE does not have any side effects; it also makes no sense to mark it ↵Evan Cheng
cheap as a copy. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123031 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-07Add ARM patterns to match EXTRACT_SUBVECTOR nodes.Bob Wilson
Also fix an off-by-one in SelectionDAGBuilder that was preventing shuffle vectors from being translated to EXTRACT_SUBVECTOR. Patch by Tim Northover. The test changes are needed to keep those spill-q tests from testing aligned spills and restores. If the only aligned stack objects are spill slots, we no longer realign the stack frame. Prior to this patch, an EXTRACT_SUBVECTOR was legalized by loading from the stack, which created an aligned frame index. Now, however, there is nothing except the spill slot in the stack frame, so I added an aligned alloca. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122995 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-06Re-implement r122936 with proper target hooks. Now getMaxStoresPerMemcpyEvan Cheng
etc. takes an option OptSize. If OptSize is true, it would return the inline limit for functions with attribute OptSize. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122952 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-24Various bits of framework needed for precise machine-level selectionAndrew Trick
DAG scheduling during isel. Most new functionality is currently guarded by -enable-sched-cycles and -enable-sched-hazard. Added InstrItineraryData::IssueWidth field, currently derived from ARM itineraries, but could be initialized differently on other targets. Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is active, and if so how many cycles of state it holds. Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry into the scheduler's available queue. ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to get information about it's SUnits, provides RecedeCycle for bottom-up scheduling, correctly computes scoreboard depth, tracks IssueCount, and considers potential stall cycles when checking for hazards. ScheduleDAGRRList now models machine cycles and hazards (under flags). It tracks MinAvailableCycle, drives the hazard recognizer and priority queue's ready filter, manages a new PendingQueue, properly accounts for stall cycles, etc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122541 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-24whitespaceAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122539 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-23Flag -> Glue, the ongoing sagaChris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122513 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-18Remove the MCObjectFormat class.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122147 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-17During local stack slot allocation, the materializeFrameBaseRegister functionBill Wendling
may be called. If the entry block is empty, the insertion point iterator will be the "end()" value. Calling ->getParent() on it (among others) causes problems. Modify materializeFrameBaseRegister to take the machine basic block and insert the frame base register at the beginning of that block. (It's very similar to what the code does all ready. The only difference is that it will always insert at the beginning of the entry block instead of after a previous materialization of the frame base register. I doubt that that matters here.) <rdar://problem/8782198> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122104 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-17MC/Target: Remove HasScatteredSymbols target hook variable, which has beenDaniel Dunbar
superceded and was effectively dead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122024 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-16MC: Move target specific fixup info descriptors to TargetAsmBackend instead ofDaniel Dunbar
the MCCodeEmitter, which seems like a better organization. - Also, cleaned up some magic constants while in the area. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121953 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-16MC: Make TargetAsmBackend available to the AsmStreamer.Daniel Dunbar
- Treaty talks on the non-proliferation of MC objects broke down. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121949 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14Introduce TargetRegisterInfo::getOverlaps(Reg), returning a list of allJakob Stoklund Olesen
registers that alias Reg, including itself. This is almost the same as the existing getAliasSet() method, except for the inclusion of Reg. The name matches the reflexive TRI::regsOverlap(x, y) relation. It is very common to do stuff to a register and all its aliases: stuff(Reg) for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) stuff(*Alias); That can now be written as the simpler: for (const unsigned *Alias = TRI->getOverlaps(Reg); *Alias; ++Alias) stuff(*Alias); This change requires a bit more constant space for the alias lists because Reg is included and because the empty alias list cannot be shared any longer. If the getAliasSet method is eventually removed, this space can be reclaimed by sharing overlap lists. For instance, %rax and %eax have identical overlap sets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121800 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-14Add TargetRegisterInfo::printReg() to pretty-print registers.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121780 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-10Fixed version of 121434 with no new memory leaks.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121471 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-10Revert my previous patch to make the valgrind bots happy.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121461 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-09Initial support for the cfi directives. This is just enough to getRafael Espindola
f: .cfi_startproc nop .cfi_endproc assembled (on ELF). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121434 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-08Let target asm backends see assembler flags as they go by. Use that to handleJim Grosbach
thumb vs. arm mode differences in WriteNopData(). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121219 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-06Remove the instruction fragment to data fragment lowering since it was causingRafael Espindola
freed data to be read. I will open a bug to track it being reenabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121028 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30Enable sibling call optimization of libcalls which are expanded duringEvan Cheng
legalization time. Since at legalization time there is no mapping from SDNode back to the corresponding LLVM instruction and the return SDNode is target specific, this requires a target hook to check for eligibility. Only x86 and ARM support this form of sibcall optimization right now. rdar://8707777 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120501 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-30add TLI support indicating that jumps are more expensive than logical operationsChris Lattner
and use this to disable a specific optimization. Patch by Micah Villmow! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120435 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-29Merge System into Support.Michael J. Spencer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120298 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-27Move more PEI-related hooks to TFIAnton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120229 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-27Move callee-saved regs spills / reloads to TFIAnton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120228 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-26Remove the unused TheTarget member.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120168 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-23Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept.Wesley Peck
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119990 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-20Move some more hooks to TargetFrameInfoAnton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119904 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-19Prefetch has a MemOperand now. FileCheckize a test.Dale Johannesen
This finishes up 8460971. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119848 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-19Change some methods in MCDwarf.cpp to be able to handle an arbitraryRafael Espindola
MCStreamer instead of just MCObjectStreamer. Address changes cannot be as efficient as we have to use DW_LNE_set_addres, but at least most of the logic is shared. This will be used so that, with CodeGen still using EmitDwarfLocDirective, llvm-gcc is able to produce debug_line sections without needing an assembler that supports .loc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119777 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-18Move getInitialFrameState() to TargetFrameInfoAnton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119754 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-18Move hasFP() and few related hooks to TargetFrameInfo.Anton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119740 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-17Remove ARM isel hacks that fold large immediates into a pair of add, sub, and,Evan Cheng
and xor. The 32-bit move immediates can be hoisted out of loops by machine LICM but the isel hacks were preventing them. Instead, let peephole optimization pass recognize registers that are defined by immediates and the ARM target hook will fold the immediates in. Other changes include 1) do not fold and / xor into cmp to isel TST / TEQ instructions if there are multiple uses. This happens when the 'and' is live out, machine sink would have sinked the computation and that ends up pessimizing code. The peephole pass would recognize situations where the 'and' can be toggled to define CPSR and eliminate the comparison anyway. 2) Move peephole pass to after machine LICM, sink, and CSE to avoid blocking important optimizations. rdar://8663787, rdar://8241368 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119548 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-17make isVirtualSection a virtual method on MCSection. Chris' suggestion.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119547 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15Code clean up. The peephole pass should be the one updating the instructionEvan Cheng
iterator, not TII->OptimizeCompareInstr. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119186 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15add fields to the .td files unconditionally, simplifying tblgen a bit.Chris Lattner
Switch the ARM backend to use 'let' instead of 'set' with this change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119120 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15First step of huge frame-related refactoring: move emit{Prologue,Epilogue} ↵Anton Korobeynikov
out of TargetRegisterInfo to TargetFrameInfo, which is definitely much better suitable place git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119097 91177308-0d34-0410-b5e6-96231b3b80d8
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