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2011-04-15Increase SubtargetFeatureKV Value and Implies fields to 64 bits since some ↵Evan Cheng
targets are getting very close to 32 subtarget features. Also teach tablegen to error when there are more than 64 features to guard against undefined behavior. rdar://9282332 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129590 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-15Fix a ton of comment typos found by codespell. Patch byChris Lattner
Luis Felipe Strano Moraes! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129558 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-13Add an option to not print the alias of an instruction. It defaults to "printBill Wendling
the alias". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129485 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-13Recommit r129383. PreRA scheduler heuristic fixes: VRegCycle, TokenFactor ↵Andrew Trick
latency. Additional fixes: Do something reasonable for subtargets with generic itineraries by handle node latency the same as for an empty itinerary. Now nodes default to unit latency unless an itinerary explicitly specifies a zero cycle stage or it is a TokenFactor chain. Original fixes: UnitsSharePred was a source of randomness in the scheduler: node priority depended on the queue data structure. I rewrote the recent VRegCycle heuristics to completely replace the old heuristic without any randomness. To make the ndoe latency adjustments work, I also needed to do something a little more reasonable with TokenFactor. I gave it zero latency to its consumers and always schedule it as low as possible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129421 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-08Change -arm-trap-func= into a non-arm specific option. Now Intrinsic::trap ↵Evan Cheng
is lowered into a call to the specified trap function at sdisel time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129152 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-07Change -arm-divmod-libcall to a target neutral option.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129045 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-02Add a RemoveFromWorklist method to DCI. This is needed to do some complicatedCameron Zwarich
transformations in target-specific DAG combines without causing DAGCombiner to delete the same node twice. If you know of a better way to avoid this (see my next patch for an example), please let me know. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128758 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-28Integrated-As: Add support for setting the AllowTemporaryLabels flag viaDaniel Dunbar
integrated-as. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128431 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-21Fix unused param warning.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128005 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-21We need to pass the TargetMachine object to the InstPrinter if we are printingBill Wendling
the alias of an InstAlias instead of the thing being aliased. Because we need to know the features that are valid for an InstAlias. This is part of a work-in-progress. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127986 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-21Re-apply r127953 with fixes: eliminate empty return block if it has no ↵Evan Cheng
predecessors; update dominator tree if cfg is modified. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127981 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-19Revert r127953, "SimplifyCFG has stopped duplicating returns into predecessorsDaniel Dunbar
to canonicalize IR", it broke a lot of things. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127954 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-19SimplifyCFG has stopped duplicating returns into predecessors to canonicalize IREvan Cheng
to have single return block (at least getting there) for optimizations. This is general goodness but it would prevent some tailcall optimizations. One specific case is code like this: int f1(void); int f2(void); int f3(void); int f4(void); int f5(void); int f6(void); int foo(int x) { switch(x) { case 1: return f1(); case 2: return f2(); case 3: return f3(); case 4: return f4(); case 5: return f5(); case 6: return f6(); } } => LBB0_2: ## %sw.bb callq _f1 popq %rbp ret LBB0_3: ## %sw.bb1 callq _f2 popq %rbp ret LBB0_4: ## %sw.bb3 callq _f3 popq %rbp ret This patch teaches codegenprep to duplicate returns when the return value is a phi and where the phi operands are produced by tail calls followed by an unconditional branch: sw.bb7: ; preds = %entry %call8 = tail call i32 @f5() nounwind br label %return sw.bb9: ; preds = %entry %call10 = tail call i32 @f6() nounwind br label %return return: %retval.0 = phi i32 [ %call10, %sw.bb9 ], [ %call8, %sw.bb7 ], ... [ 0, %entry ] ret i32 %retval.0 This allows codegen to generate better code like this: LBB0_2: ## %sw.bb jmp _f1 ## TAILCALL LBB0_3: ## %sw.bb1 jmp _f2 ## TAILCALL LBB0_4: ## %sw.bb3 jmp _f3 ## TAILCALL rdar://9147433 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127953 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-18Beginnings of MC-JIT code generation.Jim Grosbach
Proof-of-concept code that code-gens a module to an in-memory MachO object. This will be hooked up to a run-time dynamic linker library (see: llvm-rtdyld for similarly conceptual work for that part) which will take the compiled object and link it together with the rest of the system, providing back to the JIT a table of available symbols which will be used to respond to the getPointerTo*() queries. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127916 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-17Move more logic into getTypeForExtArgOrReturn.Cameron Zwarich
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127809 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-17Rename getTypeForExtendedInteger() to getTypeForExtArgOrReturn().Cameron Zwarich
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127807 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-16The x86-64 ABI says that a bool is only guaranteed to be sign-extended to a byteCameron Zwarich
rather than an int. Thankfully, this only causes LLVM to miss optimizations, not generate incorrect code. This just fixes the zext at the return. We still insert an i32 ZextAssert when reading a function's arguments, but it is followed by a truncate and another i8 ZextAssert so it is not optimized. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127766 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-16Add TargetData::fitsInLegalInteger().Cameron Zwarich
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127714 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15- Add "Bitcast" target instruction property for instructions which performEvan Cheng
nothing more than a bitcast. - Teach tablegen to automatically infer "Bitcast" property. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127667 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-10Re-commit 127368 and 127371. They are exonerated.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127380 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-09Revert 127368 and 127371 for now.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127376 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-09Restore the default implementation of getCrossCopyRegClass: no need for ↵Evan Cheng
cross-regclass copies. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127371 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-09Change the definition of TargetRegisterInfo::getCrossCopyRegClass to be moreEvan Cheng
flexible. If it returns a register class that's different from the input, then that's the register class used for cross-register class copies. If it returns a register class that's the same as the input, then no cross- register class copies are needed (normal copies would do). If it returns null, then it's not at all possible to copy registers of the specified register class. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127368 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-09Add createELFObjectTargetWriter method to TargetAsmBackend, which enables ↵Jan Sjödin
construction of non-standard ELFObjectWriters that can be used in MCJIT. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127346 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-09Add InitializeNativeAsmParser function.Jan Sjödin
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127341 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-07Move getRegPressureLimit() from TargetLoweringInfo to TargetRegisterInfo.Cameron Zwarich
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127175 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-05Missing "virtual" keyword. Jakob's review.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127070 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-05Increased the register pressure limit on x86_64 from 8 to 12Andrew Trick
regs. This is the only change in this checkin that may affects the default scheduler. With better register tracking and heuristics, it doesn't make sense to artificially lower the register limit so much. Added -sched-high-latency-cycles and X86InstrInfo::isHighLatencyDef to give the scheduler a way to account for div and sqrt on targets that don't have an itinerary. It is currently defaults to 10 (the actual number doesn't matter much), but only takes effect on non-default schedulers: list-hybrid and list-ilp. Added several heuristics that can be individually disabled for the non-default sched=list-ilp mode. This helps us determine how much better we can do on a given benchmark than the default scheduler. Certain compute intensive loops run much faster in this mode with the right set of heuristics, and it doesn't seem to have much negative impact elsewhere. Not all of the heuristics are needed, but we still need to experiment to decide which should be disabled by default for sched=list-ilp. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127067 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-03Allow a target to choose whether to prefer the scavenger emergency spill slotJim Grosbach
be next to the frame pointer or the stack pointer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126956 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-03Optimize fprintf -> iprintf if there are no floating point argumentsRichard Osborne
and siprintf is available on the target. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126940 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-03Optimize sprintf -> siprintf if there are no floating point argumentsRichard Osborne
and siprintf is available on the target. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126937 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-03Optimize printf -> iprintf if there are no floating point argumentsRichard Osborne
and iprintf is available on the target. Currently iprintf is only marked as being available on the XCore. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126935 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-28Fix warning when building with clang++.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126679 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-28Support for byval parameters on ARM. Will be enabled by a forthcomingStuart Hastings
patch to the front-end. Radar 7662569. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126655 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-25Allow targets to specify a the type of the RHS of a shift parameterized on ↵Owen Anderson
the type of the LHS. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126518 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-24Rewrite the vector part of getExtendedTypeAction to make it moreDuncan Sands
understandable (at least I find it easier to understand like this). No intended functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126382 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-18add a way to disable all builtins, wire it up to opt's ↵Chris Lattner
-disable-simplifylibcalls flag. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125978 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-18add memset and memcpy, though they are always available for now.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125973 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-18Add FixedLenDecoderEmitter, the skeleton of a new disassembler emitter for ↵Owen Anderson
fixed-length instruction encodings. A major part of its (eventual) goal is to support a much cleaner separation between disassembly callbacks provided by the target and the disassembler emitter itself, i.e. not requiring hardcoding of knowledge in tblgen like the existing disassembly emitters do. The hope is that some day this will allow us to replace the existing non-Thumb ARM disassembler and remove some of the hacks the old one introduced to tblgen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125966 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-18introduce a new TargetLibraryInfo pass, which transformations can use toChris Lattner
query about available library functions. For now this just has memset_pattern16, which exists on darwin, but it can be extended for a bunch of other things in the future. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125965 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-11Remove std::string version of getNameWithPrefix.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125363 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-10Clean trailing whitespace.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125304 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-07Implement support for custom target specific asm parsing of operands.Bruno Cardoso Lopes
Motivation: Improve the parsing of not usual (different from registers or immediates) operand forms. This commit implements only the generic support. The ARM specific modifications will come next. A table like the one below is autogenerated for every instruction containing a 'ParserMethod' in its AsmOperandClass static const OperandMatchEntry OperandMatchTable[20] = { /* Mnemonic, Operand List Mask, Operand Class, Features */ { "cdp", 29 /* 0, 2, 3, 4 */, MCK_Coproc, Feature_IsThumb|Feature_HasV6 }, { "cdp", 58 /* 1, 3, 4, 5 */, MCK_Coproc, Feature_IsARM }, A matcher function very similar (but lot more naive) to MatchInstructionImpl scans the table. After the mnemonic match, the features are checked and if the "to be parsed" operand index is present in the mask, there's a real match. Then, a switch like the one below dispatch the parsing to the custom method provided in 'ParseMethod': case MCK_Coproc: return TryParseCoprocessorOperandName(Operands); git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125030 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-04MC/AsmMatcher: Add support for custom conversion functions.Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124870 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-02Given a pair of floating point load and store, if there are no other uses ofEvan Cheng
the load, then it may be legal to transform the load and store to integer load and store of the same width. This is done if the target specified the transformation as profitable. e.g. On arm, this can transform: vldr.32 s0, [] vstr.32 s0, [] to ldr r12, [] str r12, [] rdar://8944252 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124708 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-02Fix comment typo.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124705 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-27Introduce virtual ParseRegister method in TargetAsmParser.Roman Divacky
Create override of this method in X86/ARM/MBlaze. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124378 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-26[AVX] Add INSERT_SUBVECTOR and support it on x86. This provides aDavid Greene
default implementation for x86, going through the stack in a similr fashion to how the codegen implements BUILD_VECTOR. Eventually this will get matched to VINSERTF128 if AVX is available. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124307 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-26[AVX] Support EXTRACT_SUBVECTOR on x86. This provides a defaultDavid Greene
implementation of EXTRACT_SUBVECTOR for x86, going through the stack in a similr fashion to how the codegen implements BUILD_VECTOR. Eventually this will get matched to VEXTRACTF128 if AVX is available. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124292 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-25[AVX] Fix a typo in the extract subvector type constraints to specifyDavid Greene
the correct number of operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124234 91177308-0d34-0410-b5e6-96231b3b80d8
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