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2011-06-12Bugfix: When looking for a legal vector type, stop looking when a non-simpleNadav Rotem
element type is found. This fix addresses some of the tests in Duncan's testcase (forthcoming). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132891 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-12Tweak hash function and compress hash tables.Jakob Stoklund Olesen
Make the hash tables as small as possible while ensuring that all lookups can be done in less than 8 probes. Cut the aliases hash table in half by only storing a < b pairs - it is a symmetric relation. Use larger multipliers on the initial hash function to ensure that it properly covers the whole table, and to resolve some clustering in the very regular ARM register bank. This reduces the size of most of these tables by 4x - 8x. For instance, the ARM tables shrink from 48 KB to 8 KB. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132888 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-12Compute lists of sub-regs, super-regs, and overlapping regs.Jakob Stoklund Olesen
Besides moving structural computations to CodeGenRegisters.cpp, this also well-defines the order of these lists: - Sub-register lists come from a pre-order traversal of the graph defined by the SubRegs lists in the .td files. - Super-register lists are topologically ordered so no register comes before any of its sub-registers. When the sub-register graph is not a tree, independent super-registers appear in numerical order. - Lists of overlapping registers are ordered according to register number. This reverses the order of the super-regs lists, but nobody was depending on that. The previous order of the overlaps lists was odd, and it may have depended on the precise behavior of std::stable_sort. The old computations are still there, but will be removed shortly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132881 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-08Add a parameter to CCState so that it can access the MachineFunction.Eric Christopher
No functional change. Part of PR6965 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132763 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02Have LowerOperandForConstraint handle multiple character constraints.Eric Christopher
Part of rdar://9119939 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132510 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02Make it possible to have unallocatable register classes.Jakob Stoklund Olesen
Some register classes are only used for instruction operand constraints. They should never be used for virtual registers. Previously, those register classes were given an empty allocation order, but now you can say 'let isAllocatable=0' in the register class definition. TableGen calculates if a register is part of any allocatable register class, and makes that information available in TargetRegisterDesc::inAllocatableClass. The goal here is to eliminate use cases for overriding allocation_order_* methods. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132508 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-01Initialize IssueWidth to zero.Benjamin Kramer
Fixes valgrind errors in the CellSPU backend. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132405 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-01Fix PR10059 and future variations by handling all register subclasses.Jakob Stoklund Olesen
Add TargetRegisterInfo::hasSubClassEq and use it to check for compatible register classes instead of trying to list all register classes in X86's getLoadStoreRegOpcode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132398 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-01This patch is another step in the direction of adding vector select. In thisNadav Rotem
patch we add a flag to enable a new type legalization decision - to promote integer elements in vectors. Currently, the rest of the codegen does not support this kind of legalization. This flag will be removed when the transition is complete. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132394 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-01FGETSIGN support for x86, using movmskps/pd. Will be enabled with aStuart Hastings
patch to TargetLowering.cpp. rdar://problem/5660695 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132388 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-30Use the dwarf->llvm mapping to print register names in the cfiRafael Espindola
directives. Fixes PR9826. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132317 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-30Introduce the DwarfRegAlias class for declaring that two registers have theRafael Espindola
same dwarf number. This will be used for creating a dwarf number to register mapping. The only case that needs this so far is the XMM/YMM registers that unfortunately do have the same numbers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132314 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-28Refactor the type legalizer. Switch TargetLowering to a new enum - ↵Nadav Rotem
LegalizeTypeAction. This patch does not change the behavior of the type legalizer. The codegen produces the same code. This infrastructural change is needed in order to enable complex decisions for vector types (needed by the vector-select patch). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132263 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-27Refactor getActionType and getTypeToTransformTo ; place all of the 'decision'Nadav Rotem
code in one place. Re-apply 131534 and fix the multi-step promotion of integers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132217 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-27Add a parameter to the Win64 EH section getters to get a section with aCharles Davis
suffix (e.g. .xdata$myfunc). The suffix part isn't implemented yet, but I'll get to it in the next patch. Fix up all callers of the affected functions. Make them pass said suffix to the function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132205 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25Replace the -unwind-tables option with a per function flag. This is moreRafael Espindola
LTO friendly as we can now correctly merge files compiled with or without -fasynchronous-unwind-tables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132033 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-24Implement the rest of the SEH directive-parsing methods in the COFFAsmParser.Charles Davis
Add a size alignment check to the .seh_stackalloc directive parser. Add a more descriptive error message to the .seh_handler directive parser. Add methods to the TargetAsmInfo struct in support of all this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131992 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-24Add a method to TargetRegisterInfo to get the register number that the Win64 EHCharles Davis
scheme uses internally. Implement it for x86 (the only architecture that LLVM supports for which this matters right now). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131969 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-24Work around code generation bug in Visual Studio 2010.Jakob Stoklund Olesen
See http://llvm.org/pr9976 for details. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131954 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-22Allow access to the .pdata and .xdata sections through the TargetAsmInfoCharles Davis
class. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131816 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-21add a copy ctor to TargetLibraryInfo.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131806 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-20Add .pdata and .xdata sections to the COFF TLOF implementation.Charles Davis
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131763 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-18Revert commit 131534 since it seems to have broken several buildbots.Duncan Sands
Original log entry: Refactor getActionType and getTypeToTransformTo ; place all of the 'decision' code in one place. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131536 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-18Refactor getActionType and getTypeToTransformTo ; place all of the 'decision'Nadav Rotem
code in one place. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131534 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-10Add support for producing .deubg_frame sections.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131121 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-07Fix comments per Duncan's review.Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131055 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-06Make the logic for determining function alignment more explicit. No ↵Eli Friedman
functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131012 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-05Remove a flag that would set the ".eh" symbol as .globl. MachO was the only oneBill Wendling
who used this flag, and it now emits CFI and doesn't emit this anymore. All other targets left this flag "false". <rdar://problem/8486371> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130918 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-03Add an unfolded offset field to LSR's Formula record. This is used toDan Gohman
model constants which can be added to base registers via add-immediate instructions which don't require an additional register to materialize the immediate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130743 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-01enhance memcpyopt to obey -fno-builtin and friends. This addresses aChris Lattner
problem reported on cfe-dev. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130661 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-01GCC uses a different encoding of pointers in the FDE when usingRafael Espindola
-fno-dwarf2-cfi-asm. Implement the same behavior. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130637 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-30Add all the plumbing needed for MC to expand cfi to the old tables inRafael Espindola
the final assembly. It is the same technique used when targeting assemblers that don't support .loc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130587 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-28Let the immediate leaf pattern take transforms and switch the signedEric Christopher
immediate patterns in arm to using the pattern. Handles rdar://9299434 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130386 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-28Forward isFunctionEHFrameSymbolPrivate. If it is false, produce the foo.ehRafael Espindola
symbols. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130375 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-27Remove unnecessary argument.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130343 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-27Rename getPersonalityPICSymbol to getCFIPersonalitySymbol, document it, andRafael Espindola
give it a bit more responsibility. Also implement it for MachO. If hacked to use cfi, 32 bit MachO will produce .cfi_personality 155, L___gxx_personality_v0$non_lazy_ptr and 64 bit will produce .cfi_presonality ___gxx_personality_v0 The general idea is that .cfi_personality gets passed the final symbol. It is up to codegen to produce it if using indirect representation (like 32 bit MachO), but it is up to MC to decide which relocations to create. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130341 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-26Add a TRI::getLargestLegalSuperClass hook to provide an upper limit on ↵Jakob Stoklund Olesen
register class inflation. The hook will be used by the register allocator when recomputing register classes after removing constraints. Thumb1 code doesn't allow anything larger than tGPR, and x86 needs to ensure that the spill size doesn't change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130228 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-22include/llvm/Target/TargetAsmInfo.h: Fix a warning.NAKAMURA Takumi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129972 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-22Compute the size of the FDE encoding instead of hard coding it. UpdateRafael Espindola
X8664_ELFTargetObjectFile::getFDEEncoding to match reality. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129959 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-21Don't allow per-register spill size and alignment.Jakob Stoklund Olesen
These values were not used for anything. Spill size and alignment is a property of the register class, not the register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129906 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-20Remove -use-divmod-libcall. Let targets opt in when they are available.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129884 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-20Prefer cheap registers for busy live ranges.Jakob Stoklund Olesen
On the x86-64 and thumb2 targets, some registers are more expensive to encode than others in the same register class. Add a CostPerUse field to the TableGen register description, and make it available from TRI->getCostPerUse. This represents the cost of a REX prefix or a 32-bit instruction encoding required by choosing a high register. Teach the greedy register allocator to prefer cheap registers for busy live ranges (as indicated by spill weight). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129864 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-20ARM byval support. Will be enabled by another patch to the FE. ↵Stuart Hastings
<rdar://problem/7662569> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129858 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-20Remove unused arguments.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129844 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-19Avoid write-after-write issue hazards for Cortex-A9.Bob Wilson
Add a avoidWriteAfterWrite() target hook to identify register classes that suffer from write-after-write hazards. For those register classes, try to avoid writing the same register in two consecutive instructions. This is currently disabled by default. We should not spill to avoid hazards! The command line flag -avoid-waw-hazard can be used to enable waw avoidance. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129772 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-18Add a new bit that ImmLeaf's can opt into, which allows them to duck out ofChris Lattner
the generated FastISel. X86 doesn't need to generate code to match ADD16ri8 since ADD16ri will do just fine. This is a small codesize win in the generated instruction selector. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129692 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-17since the VT is fixed for a ImmLeaf, there is no reason to expose it to the ↵Chris Lattner
matching code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129677 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-17now that predicates have a decent abstraction layer on them, introduce a new Chris Lattner
kind of predicate: one that is specific to imm nodes. The predicate function specified here just checks an int64_t directly instead of messing around with SDNode's. The virtue of this is that it means that fastisel and other things can reason about these predicates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129675 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-17Rework our internal representation of node predicates to expose moreChris Lattner
structure and fix some fixmes. We now have a TreePredicateFn class that handles all of the decoding of these things. This is an internal cleanup that has no impact on the code generated by tblgen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129670 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-16Put each personality function in a section. This fixes the gnu ld warning:Rafael Espindola
error in foo.o; no .eh_frame_hdr table will be created. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129635 91177308-0d34-0410-b5e6-96231b3b80d8
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