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2011-09-11CR fixes per Bruno's request.Nadav Rotem
Undo the changes from r139285 which added custom lowering to vselect. Add tablegen lowering for vselect. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139479 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-06Add codegen support for vector select (in the IR this means a selectDuncan Sands
with a vector condition); such selects become VSELECT codegen nodes. This patch also removes VSETCC codegen nodes, unifying them with SETCC nodes (codegen was actually often using SETCC for vector SETCC already). This ensures that various DAG combiner optimizations kick in for vector comparisons. Passes dragonegg bootstrap with no testsuite regressions (nightly testsuite as well as "make check-all"). Patch mostly by Nadav Rotem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139159 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-30Emit segmented-stack specific code into function prologues forRafael Espindola
X86. Modify the pass added in the previous patch to call this new code. This new prologues generated will call a libgcc routine (__morestack) to allocate more stack space from the heap when required Patch by Sanjoy Das. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138812 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-30Command line option to enable support for segmented stacks:Rafael Espindola
-segmented-stacks. Patch by Sanjoy Das! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138811 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-30Follow up to r138791.Evan Cheng
Add a instruction flag: hasPostISelHook which tells the pre-RA scheduler to call a target hook to adjust the instruction. For ARM, this is used to adjust instructions which may be setting the 's' flag. ADC, SBC, RSB, and RSC instructions have implicit def of CPSR (required since it now uses CPSR physical register dependency rather than "glue"). If the carry flag is used, then the target hook will *fill in* the optional operand with CPSR. Otherwise, the hook will remove the CPSR implicit def from the MachineInstr. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138810 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24Basic x86 code generation for atomic load and store instructions.Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138478 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24Move TargetRegistry and TargetSelect from Target to Support where they belong.Evan Cheng
These are strictly utilities for registering targets and components. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138450 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-23Some refactoring so TargetRegistry.h no longer has to include any filesEvan Cheng
from MC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138367 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-09Trim an unneeded header.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137184 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-08Hoist hasLoadFromStackSlot and hasStoreToStackSlot.Jakob Stoklund Olesen
These the methods are target-independent since they simply scan the memory operands. They can live in TargetInstrInfoImpl. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137063 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-08Add MCInstrAnalysis class. This allows the targets to specify own versions ↵Benjamin Kramer
of MCInstrDescs functions. - Add overrides for ARM. - Teach llvm-objdump to use this instead of plain MCInstrDesc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137059 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-04Fix a place that was clearly forgotten when the type legalizationDuncan Sands
logic moved over to its own enum. Noticed by Andrey Karpov with the PVS-studio tool. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136881 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-03New approach to r136737: insert the necessary fences for atomic ops in ↵Eli Friedman
platform-independent code, since a bunch of platforms (ARM, Mips, PPC, Alpha are the relevant targets here) need to do essentially the same thing. I think this completes the basic CodeGen for atomicrmw and cmpxchg. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136813 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-27Code generation for 'fence' instruction.Eli Friedman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136283 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26Rename createCodeEmitter to createMCCodeEmitter; createObjectStreamer to ↵Evan Cheng
createMCObjectStreamer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136031 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-26Rename TargetAsmParser to MCTargetAsmParser and TargetAsmLexer to ↵Evan Cheng
MCTargetAsmLexer; rename createAsmLexer to createMCAsmLexer and createAsmParser to createMCAsmParser. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136027 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-25Rename TargetAsmBackend to MCAsmBackend; rename createAsmBackend to ↵Evan Cheng
createMCAsmBackend. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136010 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-25Fix last bits of MC layer issues. llvm-mc doesn't need to initialize ↵Evan Cheng
TargetMachine's anymore. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135963 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-23Turn the DenseSet in MCRegisterClass into a tblgenerated bit field. This ↵Benjamin Kramer
should be faster and smaller. Goodbye static ctors and dtors! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135836 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-23Give TargetRegisterClass a pointer to the MCRegisterClass and use it to ↵Benjamin Kramer
access its data. This makes TargetRegisterClass slightly slower. Next step will be making contains faster. Eventually TargetRegisterClass will be killed entirely. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135835 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-23Move TargetAsmParser.h TargetAsmBackend.h and TargetAsmLexer.h to MC where ↵Evan Cheng
they belong. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135833 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22Combine all MC initialization routines into one. e.g. InitializeX86MCAsmInfo,Evan Cheng
InitializeX86MCInstrInfo, etc. are combined into InitializeX86TargetMC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135812 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22Move the logic for printing the registered targets into a staticChandler Carruth
function on the TargetRegistry. Also clean it up and use the modern LLVM utility libraries available instead of rolling a few things manually. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135756 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-22Teach tblgen to emit MCRegisterClasses.Benjamin Kramer
- This currently introduces more instances of the static DenseSet dtor, but that should be fixable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135735 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-21Sink parts of TargetRegisterClass into MCRegisterClass.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135683 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-20Remove the now defunct getCompactUnwindEncoding method from the frame ↵Bill Wendling
lowering code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135634 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-20Goodbye TargetAsmInfo. This eliminate last bit of CodeGen and Target in llvm-mc.Evan Cheng
There is still a bit more refactoring left to do in Targets. But we are now very close to fixing all the layering issues in MC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135611 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-20- Move CodeModel from a TargetMachine global option to MCCodeGenInfo.Evan Cheng
- Introduce JITDefault code model. This tells targets to set different default code model for JIT. This eliminates the ugly hack in TargetMachine where code model is changed after construction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135580 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-20Add MCObjectFileInfo and sink the MCSections initialization code fromEvan Cheng
TargetLoweringObjectFileImpl down to MCObjectFileInfo. TargetAsmInfo is done to one last method. It's *almost* gone! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135569 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-19Enhance the FixedLengthDecoder to be able to generate plausible-looking ↵Owen Anderson
decoders for ARM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135524 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-19Convert TargetData::getIndexedOffset to use ArrayRef.Jay Foad
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135478 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-19Introduce MCCodeGenInfo, which keeps information that can affect codegenEvan Cheng
(including compilation, assembly). Move relocation model Reloc::Model from TargetMachine to MCCodeGenInfo so it's accessible even without TargetMachine. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135468 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-19Make isLoadExtLegal and isTruncStoreLegal check what the name says. :) This ↵Eli Friedman
might have some minor effect on CellSPU, but all other targets should be unaffected. Fixing per report from Damien Vincent on llvmdev. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135462 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-18Eliminate TargetAsmInfo::getCompactUnwindEncoding. This get rid of theEvan Cheng
use of TargetFrameLowering in TargetAsmInfo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135439 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-18Move getInitialFrameState from TargetFrameInfo to MCAsmInfo (suggestions forEvan Cheng
better location welcome). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135438 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-18Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo downEvan Cheng
to MCRegisterInfo. Also initialize the mapping at construction time. This patch eliminate TargetRegisterInfo from TargetAsmInfo. It's another step towards fixing the layering violation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135424 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-18Migrate LLVM and Clang to use the new makeArrayRef(...) functions where ↵Frits van Bommel
previously explicit non-default constructors were used. Mostly mechanical with some manual reformatting. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135390 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-18land David Blaikie's patch to de-constify Type, with a few tweaks.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135375 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-15remove the InvalidateStructLayoutInfo API, which is dead and unnecessary nowChris Lattner
that type refinement is toast. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135245 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-15Move some parts of TargetAsmInfo down to MCAsmInfo. This is not the greatestEvan Cheng
solution but it is a small step towards removing the horror that is TargetAsmInfo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135237 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14Rename createAsmInfo to createMCAsmInfo and move registration code to ↵Evan Cheng
MCTargetDesc to prepare for next round of changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135219 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14Add a new field to MCOperandInfo that contains information about the type of ↵Benjamin Kramer
the Operand. - The actual values are from the MCOI::OperandType enum. - Teach tblgen to read it from the instruction definition. - This is a better implementation of the hacks in edis. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135197 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-13Add a target-indepedent entry to MCInstrDesc to describe the encoded size of ↵Owen Anderson
an opcode. Switch ARM over to using that rather than its own special MCInstrDesc bits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135106 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-12There is a cyclic dependency between MC and Target if this method is ↵Bill Wendling
out-of-line. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135006 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-12Remove IntegerType constness from TargetDataTobias Grosser
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134978 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-12Revert r134893 and r134888 (and related patches in other trees). It was causingBill Wendling
an assert on Darwin llvm-gcc builds. Assertion failed: (castIsValid(op, S, Ty) && "Invalid cast!"), function Create, file /Users/buildslave/zorg/buildbot/smooshlab/slave-0.8/build.llvm-gcc-i386-darwin9-RA/llvm.src/lib/VMCore/Instructions.cpp, li\ ne 2067. etc. http://smooshlab.apple.com:8013/builders/llvm-gcc-i386-darwin9-RA/builds/2354 --- Reverse-merging r134893 into '.': U include/llvm/Target/TargetData.h U include/llvm/DerivedTypes.h U tools/bugpoint/ExtractFunction.cpp U unittests/Support/TypeBuilderTest.cpp U lib/Target/ARM/ARMGlobalMerge.cpp U lib/Target/TargetData.cpp U lib/VMCore/Constants.cpp U lib/VMCore/Type.cpp U lib/VMCore/Core.cpp U lib/Transforms/Utils/CodeExtractor.cpp U lib/Transforms/Instrumentation/ProfilingUtils.cpp U lib/Transforms/IPO/DeadArgumentElimination.cpp U lib/CodeGen/SjLjEHPrepare.cpp --- Reverse-merging r134888 into '.': G include/llvm/DerivedTypes.h U include/llvm/Support/TypeBuilder.h U include/llvm/Intrinsics.h U unittests/Analysis/ScalarEvolutionTest.cpp U unittests/ExecutionEngine/JIT/JITTest.cpp U unittests/ExecutionEngine/JIT/JITMemoryManagerTest.cpp U unittests/VMCore/PassManagerTest.cpp G unittests/Support/TypeBuilderTest.cpp U lib/Target/MBlaze/MBlazeIntrinsicInfo.cpp U lib/Target/Blackfin/BlackfinIntrinsicInfo.cpp U lib/VMCore/IRBuilder.cpp G lib/VMCore/Type.cpp U lib/VMCore/Function.cpp G lib/VMCore/Core.cpp U lib/VMCore/Module.cpp U lib/AsmParser/LLParser.cpp U lib/Transforms/Utils/CloneFunction.cpp G lib/Transforms/Utils/CodeExtractor.cpp U lib/Transforms/Utils/InlineFunction.cpp U lib/Transforms/Instrumentation/GCOVProfiling.cpp U lib/Transforms/Scalar/ObjCARC.cpp U lib/Transforms/Scalar/SimplifyLibCalls.cpp U lib/Transforms/Scalar/MemCpyOptimizer.cpp G lib/Transforms/IPO/DeadArgumentElimination.cpp U lib/Transforms/IPO/ArgumentPromotion.cpp U lib/Transforms/InstCombine/InstCombineCompares.cpp U lib/Transforms/InstCombine/InstCombineAndOrXor.cpp U lib/Transforms/InstCombine/InstCombineCalls.cpp U lib/CodeGen/DwarfEHPrepare.cpp U lib/CodeGen/IntrinsicLowering.cpp U lib/Bitcode/Reader/BitcodeReader.cpp git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134949 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-11De-constify Types in StructType::get() and TargetData::getIntPtrType().Jay Foad
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134893 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-11- Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfoEvan Cheng
and MCSubtargetInfo. - Added methods to update subtarget features (used when targets automatically detect subtarget features or switch modes). - Teach X86Subtarget to update MCSubtargetInfo features bits since the MCSubtargetInfo layer can be shared with other modules. - These fixes .code 16 / .code 32 support since mode switch is updated in MCSubtargetInfo so MC code emitter can do the right thing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134884 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-10Use BranchProbability instead of floating points in IfConverter.Jakub Staszak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134858 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-09Change createAsmParser to take a MCSubtargetInfo instead of triple,Evan Cheng
CPU, and feature string. Parsing some asm directives can change subtarget state (e.g. .code 16) and it must be reflected in other modules (e.g. MCCodeEmitter). That is, the MCSubtargetInfo instance must be shared. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134795 91177308-0d34-0410-b5e6-96231b3b80d8
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