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2012-10-16Merge commit '320db3f8052c9f506d9ea043ba5da534df40aa08'Derek Schuff
2012-10-16Issue:Stepan Dyatkovskiy
Stack is formed improperly for long structures passed as byval arguments for EABI mode. If we took AAPCS reference, we can found the next statements: A: "If the argument requires double-word alignment (8-byte), the NCRN (Next Core Register Number) is rounded up to the next even register number." (5.5 Parameter Passing, Stage C, C.3). B: "The alignment of an aggregate shall be the alignment of its most-aligned component." (4.3 Composite Types, 4.3.1 Aggregates). So if we have structure with doubles (9 double fields) and 3 Core unused registers (r1, r2, r3): caller should use r2 and r3 registers only. Currently r1,r2,r3 set is used, but it is invalid. Callee VA routine should also use r2 and r3 regs only. All is ok here. This behaviour is guessed by rounding up SP address with ADD+BFC operations. Fix: Main fix is in ARMTargetLowering::HandleByVal. If we detected AAPCS mode and 8 byte alignment, we waste odd registers then. P.S.: I also improved LDRB_POST_IMM regression test. Since ldrb instruction will not generated by current regression test after this patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166018 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15Merge commit 'bb20b24224734f5369d124181d086703ca439dd7'Derek Schuff
Conflicts: lib/Target/X86/X86FrameLowering.cpp lib/Target/X86/X86ISelLowering.cpp
2012-10-15Resubmit the changes to llvm core to update the functions to support ↵Micah Villmow
different pointer sizes on a per address space basis. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165941 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-12Merge commit '40573998821fde7ffeabe8507f4c9e8c7cf762f6'Derek Schuff
Conflicts: include/llvm/MC/MCAssembler.h lib/Target/ARM/ARMISelLowering.cpp lib/Target/X86/X86TargetMachine.h tools/llc/llc.cpp
2012-10-12Shuffle the virtual destructor down to the base. This should actually pacifyNick Lewycky
-Wnon-virtual-dtor for real. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165787 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-12Give this class full of virtual functions a virtual destructor. Classes loveNick Lewycky
virtual destructors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165786 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-11Merge commit '2fa8af224ea026f9432e833fd6f42a216423a010'Derek Schuff
Conflicts: lib/ExecutionEngine/JIT/JITEmitter.cpp lib/MC/MCELFStreamer.cpp lib/Target/ARM/ARMAsmPrinter.h lib/Target/X86/X86RegisterInfo.td lib/Target/X86/X86TargetMachine.cpp tools/llc/llc.cpp
2012-10-11Revert 165732 for further review.Micah Villmow
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165747 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-11Add in the first iteration of support for llvm/clang/lldb to allow variable ↵Micah Villmow
per address space pointer sizes to be optimized correctly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165726 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10Add a new interface to allow IR-level passes to access codegen-specific ↵Nadav Rotem
information. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165665 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10Issue description:Stepan Dyatkovskiy
SchedulerDAGInstrs::buildSchedGraph ignores dependencies between FixedStack objects and byval parameters. So loading byval parameters from stack may be inserted *before* it will be stored, since these operations are treated as independent. Fix: Currently ARMTargetLowering::LowerFormalArguments saves byval registers with FixedStack MachinePointerInfo. To fix the problem we need to store byval registers with MachinePointerInfo referenced to first the "byval" parameter. Also commit adds two new fields to the InputArg structure: Function's argument index and InputArg's part offset in bytes relative to the start position of Function's argument. E.g.: If function's argument is 128 bit width and it was splitted onto 32 bit regs, then we got 4 InputArg structs with same arg index, but different offset values. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165616 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10misched: Use the TargetSchedModel interface wherever possible.Andrew Trick
Allows the new machine model to be used for NumMicroOps and OutputLatency. Allows the HazardRecognizer to be disabled along with itineraries. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165603 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-09Use the attribute enums to query if a parameter has an attribute.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165550 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-09Add in the first step of the multiple pointer support. This adds in support ↵Micah Villmow
to the data layout for specifying a per address space pointer size. The next step is to update the optimizers to allow them to optimize the different address spaces with this information. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165505 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-09whitespaceNadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165475 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-08Refactor the AddrMode class out of TLI to its own header file.Nadav Rotem
This class is used by LSR and a number of places in the codegen. This is the first step in de-coupling LSR from TLI, and creating a new interface in between them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165455 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-08misched: remove the unused getSpecialAddressLatency hook.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165418 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-08Move TargetData to DataLayout.Micah Villmow
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165402 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-05Remove extraneous semicolon.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165319 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-05Implement TargetData with the DataLayout class, this will allow LLVM ↵Micah Villmow
projects to transition to DataLayout without loosing functionality. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165318 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-04This patch corrects commit 165126 by using an integer bit width instead of Preston Gurd
a pointer to a type, in order to remove the uses of getGlobalContext(). Patch by Tyler Nowicki. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165255 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-04Use attribute query methods.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165210 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-03Added instregex support to TableGen subtarget emitter.Andrew Trick
This allows the processor-specific machine model to override selected base opcodes without any fanciness. e.g. InstRW<[CoreXWriteVANDP], (instregex "VANDP")>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165180 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-01Merge commit '72f0976c1b91c7ba50dce4d0ad0289dc14d37f81'Derek Schuff
Conflicts: lib/Target/ARM/ARMISelDAGToDAG.cpp lib/Target/Mips/MipsISelLowering.cpp lib/Target/Mips/MipsSubtarget.cpp
2012-10-01TargetData: s/uint32_t/unsigned/ per Kuba's request.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164935 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-29Shrink TargetAlignElem a bit, we do a lot of searches on them.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164897 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-25Merge commit 'bc4021f31eaa97ee52655828da3e3de14a39e4a6'Derek Schuff
Conflicts: lib/MC/MCAssembler.cpp lib/Target/ARM/ARMISelDAGToDAG.cpp lib/Target/Mips/MipsInstrFPU.td lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp lib/Target/X86/X86ISelLowering.h
2012-09-25TargetLowering interface to set/get minimum block entries for jump tables.Sebastian Pop
Provide interface in TargetLowering to set or get the minimum number of basic blocks whereby jump tables are generated for switch statements rather than an if sequence. getMinimumJumpTableEntries() defaults to 4. setMinimumJumpTableEntries() allows target configuration. This patch changes the default for the Hexagon architecture to 5 as it improves performance on some benchmarks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164628 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-22Machine Model (-schedmodel only). Added SchedAliases.Andrew Trick
Allow subtargets to tie SchedReadWrite types to processor specific sequences or variants. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164451 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-19Merge commit '020aba0c3b6092e353e133446cb6453f95f0d61b'Derek Schuff
2012-09-18Fix Compile error on macDerek Schuff
Leftover from merge; mac gcc doesn't like trailing commas in enums. TBR=jvoung@chromium.org BUG= Review URL: https://codereview.chromium.org/10943021
2012-09-18Merge commit '8e70b5506ec0d7a6c2740bc89cd1b8f12a78b24f'Derek Schuff
Conflicts: include/llvm/CodeGen/ISDOpcodes.h include/llvm/Target/Target.td include/llvm/Target/TargetLowering.h include/llvm/Target/TargetOpcodes.h lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp lib/Target/Mips/MipsMCInstLower.cpp utils/TableGen/CodeGenTarget.cpp
2012-09-18TargetSchedModel API. Implement latency lookup, disabled.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164098 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-18TableGen subtarget emitter. Remove unnecessary header dependence.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164094 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-18TableGen subtarget emitter. Initialize MCSubtargetInfo with the new machine ↵Andrew Trick
model. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164092 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17Revert r164061-r164067. Most of the new subtarget emitter.Andrew Trick
I have to work out the Target/CodeGen header dependencies before putting this back. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164072 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17llvm/Target/TargetSubtargetInfo.h: Fix case in #include, ↵NAKAMURA Takumi
s#llvm/Codegen/#llvm/CodeGen#. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164070 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17TargetSchedModel API. Implement latency lookup, disabled.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164065 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17TableGen subtarget emitter. Generate resolveSchedClass generated hook for ↵Andrew Trick
resolving instruction variants. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164062 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17TableGen subtarget emitter. Initialize MCSubtargetInfo with the new machine ↵Andrew Trick
model. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164061 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17Mark unimplemented copy constructors and copy assignment operators as ↵Craig Topper
LLVM_DELETED_FUNCTION. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164016 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-14whitespaceAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163932 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-14Add in comments that explain what the indexing and the size of the arrays is ↵Micah Villmow
about. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163904 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-14misched: Generic tablegen classes for the new machine model.Andrew Trick
This is mostly documentation for the new machine model. It is designed to be flexible, easy to incrementally refine for a subtarget, and provide all the information that MachineScheduler will need. If all goes well, I will follow up with an example of the new model in use for ARM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163877 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-14commentAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163876 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-14commentAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163875 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-13The current implementation does not allow more than 32 types to be properly ↵Micah Villmow
handled with target lowering. This doubles the size to 64bit types and easily allows extension to more types. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163806 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-11Improve tblgen code cleanliness: create an unknown_class, from which the ↵Owen Anderson
unknown def inherits. Make tblgen check for that class, rather than checking for the def itself. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163664 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-11Add TRI::getSubRegIndexLaneMask().Jakob Stoklund Olesen
Sub-register lane masks are bitmasks that can be used to determine if two sub-registers of a virtual register will overlap. For example, ARM's ssub0 and ssub1 sub-register indices don't overlap each other, but both overlap dsub0 and qsub0. The lane masks will be accurate on most targets, but on targets that use sub-register indexes in an irregular way, the masks may conservatively report that two sub-register indices overlap when the eventually allocated physregs don't. Irregular register banks also mean that the bits in a lane mask can't be mapped onto register units, but the concept is similar. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163630 91177308-0d34-0410-b5e6-96231b3b80d8
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