aboutsummaryrefslogtreecommitdiff
path: root/include/llvm/Target
AgeCommit message (Collapse)Author
2012-12-05Remove two dead functions resulting from a bad rebase.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169401 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-05RegisterPressure API. Add support for physical register units.Andrew Trick
At build-time register pressure was always computed in terms of register units. But the compile-time API was expressed in terms of register classes because it was intended for virtual registers (and physical register units weren't yet used anywhere in codegen). Now that the codegen uses physreg units consistently, prepare for tracking register pressure also in terms of live units, not live registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169360 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-05Comment formatting.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169358 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-04Stack Alignment: when creating stack objects in MachineFrameInfo, make sureManman Ren
the alignment is clamped to TargetFrameLowering.getStackAlignment if the target does not support stack realignment or the option "realign-stack" is off. This will cause miscompile if the address is treated as aligned and add is replaced with or in DAGCombine. Added a bool StackRealignable to TargetFrameLowering to check whether stack realignment is implemented for the target. Also added a bool RealignOption to MachineFrameInfo to check whether the option "realign-stack" is on. rdar://12713765 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169197 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-04Remove the old TRI::ResolveRegAllocHint() and getRawAllocationOrder() hooks.Jakob Stoklund Olesen
These functions have been replaced by TRI::getRegAllocationHints() which provides the same capabilities. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169192 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-03Add a new hook for providing register allocator hints more flexibly.Jakob Stoklund Olesen
The TargetRegisterInfo::getRegAllocationHints() function is going to replace the existing mechanisms for providing target-dependent hints to the register allocator: ResolveRegAllocHint() and getRawAllocationOrder(). The new hook is more flexible because it allows the target to provide multiple preferred candidate registers for each virtual register, and it is easier to use because targets are not required to return a reference to a constant array like getRawAllocationOrder(). An optional VirtRegMap argument can be used to provide target-dependent hints that depend on the provisional assignments of other virtual registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169154 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-03Sort the #include lines for the include/... tree with the script.Chandler Carruth
AKA: Recompile *ALL* the source code! This one went much better. No manual edits here. I spot-checked for silliness and grep-checked for really broken edits and everything seemed good. It all still compiles. Yell if you see something that looks goofy. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169133 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-29Whitespace.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168937 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-29Fix 80-column violations.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168936 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-29rdar://12100355 (part 1)Shuxin Yang
This revision attempts to recognize following population-count pattern: while(a) { c++; ... ; a &= a - 1; ... }, where <c> and <a>could be used multiple times in the loop body. TODO: On X8664 and ARM, __buildin_ctpop() are not expanded to a efficent instruction sequence, which need to be improved in the following commits. Reviewed by Nadav, really appreciate! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168931 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-29Allow targets to prefer TypeSplitVector over TypePromoteInteger when ↵Justin Holewinski
computing the legalization method for vectors For some targets, it is desirable to prefer scalarizing <N x i1> instead of promoting to a larger legal type, such as <N x i32>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168882 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-29Add an MCPhysReg typedef to replace naked uint16_t.Jakob Stoklund Olesen
Use this type for arrays of physical registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168850 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-28Remove all references to TargetInstrInfoImpl.Jakob Stoklund Olesen
This class has been merged into its super-class TargetInstrInfo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168760 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-28Move the guts of TargetInstrInfoImpl into the TargetInstrInfo class.Jakob Stoklund Olesen
The *Impl class no longer serves a purpose now that the super-class implementation is in CodeGen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168759 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-27Merge commit '8d20b5f9ff609e70fae5c865931ab0f29e639d9c'Derek Schuff
Conflicts: lib/CodeGen/AsmPrinter/DwarfDebug.cpp lib/CodeGen/AsmPrinter/DwarfDebug.h lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp lib/Target/Mips/MipsISelDAGToDAG.cpp lib/Target/Mips/MipsInstrFPU.td lib/Target/Mips/MipsSubtarget.cpp lib/Target/Mips/MipsSubtarget.h lib/Target/X86/X86MCInstLower.cpp tools/Makefile tools/llc/llc.cpp
2012-11-27Make PrintReg constructor explicit to prevent weird implicit conversions ↵Craig Topper
from accidentally being triggered. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168686 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-22Add more functions to the target library information.Meador Inge
I discovered a few more missing functions while migrating optimizations from the simplify-libcalls pass to the instcombine (I already added some in r167659). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168501 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-16Work around a layering violation from Target to CodeGen.Benjamin Kramer
Technically this is still a layering violation but it's header-only which makes it less harmful. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168173 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-15Merge commit '08e9cb46feb0c8e08e3d309a0f9fd75a04ca54fb'Derek Schuff
(svn r167699, also the 3.2 branch point) Conflicts: lib/Target/X86/X86Subtarget.cpp
2012-11-13Merge commit 'be02a90de17f857ba65bbd8a11653ca1bad30adc'Derek Schuff
Conflicts: lib/Target/Mips/MipsISelLowering.cpp lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86InstrFormats.td
2012-11-14Use TARGET2 relocation for TType references on ARM.Anton Korobeynikov
Do some cleanup of the code while here. Inspired by patch by Logan Chien! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167904 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13misched: Allow subtargets to enable misched and dependent options.Andrew Trick
This allows me to begin enabling (or backing out) misched by default for one subtarget at a time. To run misched we typically want to: - Disable SelectionDAG scheduling (use the source order scheduler) - Enable more aggressive coalescing (until we decide to always run the coalescer this way) - Enable MachineScheduler pass itself. Disabling PostRA sched may follow for some subtargets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167826 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-12misched: rename interfaceto avoid gcc warningsAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167753 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-12misched: Target-independent support for MacroFusion.Andrew Trick
Uses the infrastructure from r167742 to support clustering instructure that the target processor can "fuse". e.g. cmp+jmp. Next step: target hook implementations with test cases, and enable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167744 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-12misched: Target-independent support for load/store clustering.Andrew Trick
This infrastructure is generally useful for any target that wants to strongly prefer two instructions to be adjacent after scheduling. A following checkin will add target-specific hooks with unit tests. Then this feature will be enabled by default with misched. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167742 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-10Add more functions to the target library information.Meador Inge
In the process of migrating optimizations from the simplify-libcalls pass to the instcombine pass I noticed that a few functions are missing from the target library information. These functions need to be available for querying in the instcombine library call simplifiers. More functions will probably be added in the future as more simplifiers are migrated to instcombine. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167659 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-09Revert r167620; this can be implemented using an existing CL option.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167622 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-09Add support for -mstrict-align compiler option for ARM targets.Chad Rosier
rdar://12340498 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167620 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-06Merge commit 'cfe09ed28d8a65b671e8b7a716a933e98e810e32'Derek Schuff
Conflicts: lib/Target/ARM/ARMFrameLowering.cpp lib/Target/Mips/MipsRegisterInfo.cpp lib/Target/X86/X86ISelLowering.cpp lib/Transforms/IPO/ExtractGV.cpp tools/Makefile tools/gold/gold-plugin.cpp The only interesting conflict was X86ISelLowering.ccp, which meant I had to essentially revert r167104. The problem is that we are using ESP as the stack pointer in X86ISelLowering and RSP as the stack pointer in X86FrameLowering, and that revision made them both consistently use X86RegisterInfo to determine which to use.
2012-11-05Refactor the getTypeLegalizationCost interface. No functionality change.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167422 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-05Implement the cost of abnormal x86 instruction lowering as a table.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167395 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-05PR14256: SelectionDAGLowering was renamed to SelectionDAGBuilder a long time ↵Eli Bendersky
ago. Fix references to it in documentation and comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167378 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-03X86 CostModel: Add support for a some of the common arithmetic instructions ↵Nadav Rotem
for SSE4, AVX and AVX2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167347 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-01OutputArg: added an index of the original argument to match the change toManman Ren
InputArg in r165616. This will enable us to get the actual type for both InputArg and OutputArg. rdar://9932559 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167265 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-01Generate a table-driven version of TRI::composeSubRegIndices().Jakob Stoklund Olesen
Explicitly allow composition of null sub-register indices, and handle that common case in an inlinable stub. Use a compressed table implementation instead of the previous nested switches which generated pretty bad code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167190 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-30Use TargetTransformInfo to control switch-to-lookup table transformationHans Wennborg
When the switch-to-lookup tables transform landed in SimplifyCFG, it was pointed out that this could be inappropriate for some targets. Since there was no way at the time for the pass to know anything about the target, an awkward reverse-transform was added in CodeGenPrepare that turned lookup tables back into switches for some targets. This patch uses the new TargetTransformInfo to determine if a switch should be transformed, and removes CodeGenPrepare::ConvertLoadToSwitch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167011 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-28Remove TargetELFWriterInfo.Rafael Espindola
All the credit goes to Jan Voung for noticing it was dead! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166902 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-271. Fix a bug in getTypeConversion. When a *simple* type is split, we need to ↵Nadav Rotem
return the type of the split result. 2. Change the maximum vectorization width from 4 to 8. 3. A test for both. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166864 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-26Refactor the VectorTargetTransformInfo interface.Nadav Rotem
Add getCostXXX calls for different families of opcodes, such as casts, arithmetic, cmp, etc. Port the LoopVectorizer to the new API. The LoopVectorizer now finds instructions which will remain uniform after vectorization. It uses this information when calculating the cost of these instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166836 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-26Remove the canCombineSubRegIndices() target hook.Jakob Stoklund Olesen
The new coalescer can already do all of this, so there is no need to duplicate the efforts. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166813 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-26Add VectorTargetTransform::getNumberOfParts.Hal Finkel
As discussed on IRC, add VectorTargetTransform::getNumberOfParts to provide a stable interface to the vector legalization splitting factor. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166751 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-25Merge commit 'a8a0a155de16830b8fcab539ba2ec21de3145532'Derek Schuff
Conflicts: lib/Target/X86/X86FrameLowering.cpp lib/Target/X86/X86ISelLowering.cpp The Intel folks switched some of the FrameLowering code to use X86RegisterInfo::getSlotSize isntead of pointer size, thus reducing our localmods in that file.
2012-10-25add TableGen support to create relationship maps between instructionsSebastian Pop
Relationship maps are represented as InstrMapping records which are parsed by TableGen and the information is used to construct mapping tables to represent appropriate relations between instructions. These tables are emitted into XXXGenInstrInfo.inc file along with the functions to query them. Patch by Jyotsna Verma <jverma@codeaurora.org>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166685 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-24Implement a basic cost model for vector and scalar instructions. Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166642 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-24Make LegalizeKind public so that we can use it outside of TargetLowering.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166623 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-24Implement a basic VectorTargetTransformInfo interface to be used by the loop ↵Nadav Rotem
and bb vectorizers for modeling the cost of instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166593 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-23Merge commit '92b0d8cf2c51debc7f4fb30a417ae839077a8ed0'Derek Schuff
Conflicts: lib/Target/ARM/ARMISelLowering.cpp lib/Target/Mips/MipsISelLowering.h lib/Target/X86/X86ISelLowering.h lib/Target/X86/X86TargetMachine.h tools/llc/llc.cpp The only interesting conflict was ARMISelLowering, caused by http://llvm.org/viewvc/llvm-project?view=rev&revision=166273 which actually removes a LOCALMOD for ARM byval lowering.
2012-10-18Reapply the TargerTransformInfo changes, minus the changes to LSR and ↵Nadav Rotem
Lowerinvoke. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166248 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-18Merge commit '3298959540ca744ec16b4c65db244534a929a862'Derek Schuff
Conflicts: lib/Target/X86/X86TargetMachine.h tools/llc/llc.cpp
2012-10-18Temporarily revert the TargetTransform changes.Bob Wilson
The TargetTransform changes are breaking LTO bootstraps of clang. I am working with Nadav to figure out the problem, but I am reverting it for now to get our buildbots working. This reverts svn commits: 165665 165669 165670 165786 165787 165997 and I have also reverted clang svn 165741 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166168 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2025-07-05 07:03:52 +0000