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2012-11-13Merge commit 'be02a90de17f857ba65bbd8a11653ca1bad30adc'Derek Schuff
Conflicts: lib/Target/Mips/MipsISelLowering.cpp lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86InstrFormats.td
2012-11-14Use TARGET2 relocation for TType references on ARM.Anton Korobeynikov
Do some cleanup of the code while here. Inspired by patch by Logan Chien! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167904 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13misched: Don't consider artificial edges weak edges.Andrew Trick
For now be more conservative in case other out-of-tree schedulers rely on the old behavior of artificial edges. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167808 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-12misched: Target-independent support for load/store clustering.Andrew Trick
This infrastructure is generally useful for any target that wants to strongly prefer two instructions to be adjacent after scheduling. A following checkin will add target-specific hooks with unit tests. Then this feature will be enabled by default with misched. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167742 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-12misched: Infrastructure for weak DAG edges.Andrew Trick
This adds support for weak DAG edges to the general scheduling infrastructure in preparation for MachineScheduler support for heuristics based on weak edges. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167738 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-08Add @nacl.read.tp() intrinsic, a fast version of NaCl's tls_get() IRT interfaceMark Seaborn
This is in preparation for adding an LLVM pass that will expand out TLS (thread_local) variable accesses into calls to nacl.read.tp. On ARM, there is already an arm.thread.pointer intrinsic. We reuse the code for that. On x86, we have to add an implementation. The added code is based on x86's LowerToTLSExecModel() for the %gs:0 case, and on NaCl-MIPS' LowerGlobalTLSAddress() for the __nacl_read_tp() case. (In contrast, X86NaClRewritePass.cpp inserts a __nacl_read_tp() call at the lower MI level; we don't use that approach here.) We convert LowerINTRINSIC_WO_CHAIN() into a method in order to access the Subtarget member. This is consistent with other x86 Lower methods and with the ARM version. BUG=https://code.google.com/p/nativeclient/issues/detail?id=2837 TEST="llvm-lit test/NaCl" Review URL: https://codereview.chromium.org/11383002
2012-11-07misched: Heuristics based on the machine model.Andrew Trick
misched is disabled by default. With -enable-misched, these heuristics balance the schedule to simultaneously avoid saturating processor resources, expose ILP, and minimize register pressure. I've been analyzing the performance of these heuristics on everything in the llvm test suite in addition to a few other benchmarks. I would like each heuristic check to be verified by a unit test, but I'm still trying to figure out the best way to do that. The heuristics are still in considerable flux, but as they are refined we should be rigorous about unit testing the improvements. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167527 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-07misched: handle on-the-fly regpressure queries better for 2-addrAndrew Trick
instructions without relying on liveintervals. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167526 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-06Merge commit 'cfe09ed28d8a65b671e8b7a716a933e98e810e32'Derek Schuff
Conflicts: lib/Target/ARM/ARMFrameLowering.cpp lib/Target/Mips/MipsRegisterInfo.cpp lib/Target/X86/X86ISelLowering.cpp lib/Transforms/IPO/ExtractGV.cpp tools/Makefile tools/gold/gold-plugin.cpp The only interesting conflict was X86ISelLowering.ccp, which meant I had to essentially revert r167104. The problem is that we are using ESP as the stack pointer in X86ISelLowering and RSP as the stack pointer in X86FrameLowering, and that revision made them both consistently use X86RegisterInfo to determine which to use.
2012-11-06misched: TargetSchedule interface for machine resources.Andrew Trick
Expose the processor resources defined by the machine model to the scheduler and other clients through the TargetSchedule interface. Normalize each resource count with respect to other kinds of resources. This allows scheduling heuristics to balance resources against other kinds of resources and latency. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167444 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-06ScheduleDAG interface. Added OrderKind to distinguish nonregister dependencies.Andrew Trick
This is in preparation for adding "weak" DAG edges, but generally simplifies the design. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167435 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-31Add extra declarations of hash_value needed to build llvm with xlc 12.1.Rafael Espindola
Patch by Kai! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167085 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-30[inline asm] Get the mayLoad/mayStore directly from the MIOp_ExtraInfo operand.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167050 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-30[inline asm] Implement mayLoad and mayStore for inline assembly. In general,Chad Rosier
the MachineInstr MayLoad/MayLoad flags are based on the tablegen implementation. For inline assembly, however, we need to compute these based on the constraints. Revert r166929 as this is no longer needed, but leave the test case in place. rdar://12033048 and PR13504 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167040 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-29In various places throughout the code generator, there were specialUlrich Weigand
checks to avoid performing compile-time arithmetic on PPCDoubleDouble. Now that APFloat supports arithmetic on PPCDoubleDouble, those checks are no longer needed, and we can treat the type like any other. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166958 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-26Remove GC roots that reference dead objects.Nicolas Geoffray
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166763 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-25Merge commit 'a8a0a155de16830b8fcab539ba2ec21de3145532'Derek Schuff
Conflicts: lib/Target/X86/X86FrameLowering.cpp lib/Target/X86/X86ISelLowering.cpp The Intel folks switched some of the FrameLowering code to use X86RegisterInfo::getSlotSize isntead of pointer size, thus reducing our localmods in that file.
2012-10-23Merge commit '92b0d8cf2c51debc7f4fb30a417ae839077a8ed0'Derek Schuff
Conflicts: lib/Target/ARM/ARMISelLowering.cpp lib/Target/Mips/MipsISelLowering.h lib/Target/X86/X86ISelLowering.h lib/Target/X86/X86TargetMachine.h tools/llc/llc.cpp The only interesting conflict was ARMISelLowering, caused by http://llvm.org/viewvc/llvm-project?view=rev&revision=166273 which actually removes a LOCALMOD for ARM byval lowering.
2012-10-23Use ilist rather than std::list for Node and Edge lists in the PBQP graph. ThisLang Hames
should fix an issue (described at http://stackoverflow.com/questions/10065384/instantiation-of-a-list-with-an-incomplete-type-in-a-typedef) that was preventing LLVMCodeGen from building with libc++ in C++11 mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166484 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-18Reapply the TargerTransformInfo changes, minus the changes to LSR and ↵Nadav Rotem
Lowerinvoke. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166248 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-18Merge commit '3298959540ca744ec16b4c65db244534a929a862'Derek Schuff
Conflicts: lib/Target/X86/X86TargetMachine.h tools/llc/llc.cpp
2012-10-18Change MachineFrameInfo::StackObject::Alloca from Value* to AllocaInst*Sebastian Pop
This more accurately reflects what is actually being stored in the field. No functionality change intended. Author: Matthew Curtis <mcurtis@codeaurora.org> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166215 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-18Temporarily revert the TargetTransform changes.Bob Wilson
The TargetTransform changes are breaking LTO bootstraps of clang. I am working with Nadav to figure out the problem, but I am reverting it for now to get our buildbots working. This reverts svn commits: 165665 165669 165670 165786 165787 165997 and I have also reverted clang svn 165741 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166168 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-17Switch MRI::UsedPhysRegs to a register unit bit vector.Jakob Stoklund Olesen
This is a more compact, less redundant representation, and it avoids scanning long lists of aliases for ARM D-registers, for example. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166124 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-17Add a really faster pre-RA scheduler (-pre-RA-sched=linearize). It doesn't useEvan Cheng
any scheduling heuristics nor does it build up any scheduling data structure that other heuristics use. It essentially linearize by doing a DFA walk but it does handle glues correctly. IMPORTANT: it probably can't handle all the physical register dependencies so it's not suitable for x86. It also doesn't deal with dbg_value nodes right now so it's definitely is still WIP. rdar://12474515 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166122 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-17Merge MRI::isPhysRegOrOverlapUsed() into isPhysRegUsed().Jakob Stoklund Olesen
All callers of these functions really want the isPhysRegOrOverlapUsed() functionality which also checks aliases. For historical reasons, targets without register aliases were calling isPhysRegUsed() instead. Change isPhysRegUsed() to also check aliases, and switch all isPhysRegOrOverlapUsed() callers to isPhysRegUsed(). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166117 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-17Use a SparseSet instead of a BitVector for UsedInInstr in RAFast.Jakob Stoklund Olesen
This is just as fast, and it makes it possible to avoid leaking the UsedPhysRegs BitVector implementation through MachineRegisterInfo::addPhysRegsUsed(). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166083 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-16Merge commit '320db3f8052c9f506d9ea043ba5da534df40aa08'Derek Schuff
2012-10-16Fix function parameter spelling in comments. Caught by -Wdocumentation.Dmitri Gribenko
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166024 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-16misched: Added handleMove support for updating all kill flags, not just for ↵Andrew Trick
allocatable regs. This is a medium term workaround until we have a more robust solution in the form of a register liveness utility for postRA passes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166001 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15Remove RegisterClassInfo::isReserved() and isAllocatable().Jakob Stoklund Olesen
Clients can use the equivalent functions in MRI. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165990 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15Remove LIS::isAllocatable() and isReserved() helpers.Jakob Stoklund Olesen
All callers can simply use the corresponding MRI functions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165985 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15Switch most getReservedRegs() clients to the MRI equivalent.Jakob Stoklund Olesen
Using the cached bit vector in MRI avoids comstantly allocating and recomputing the reserved register bit vector. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165983 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15Freeze the reserved registers as soon as isel is complete.Jakob Stoklund Olesen
Also provide an MRI::getReservedRegs() function to access the frozen register set, and isReserved() and isAllocatable() methods to test individual registers. The various implementations of TRI::getReservedRegs() are quite complicated, and many passes need to look at the reserved register set. This patch makes it possible for these passes to use the cached copy in MRI, avoiding a lot of malloc traffic and repeated calculations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165982 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15Merge commit 'bb20b24224734f5369d124181d086703ca439dd7'Derek Schuff
Conflicts: lib/Target/X86/X86FrameLowering.cpp lib/Target/X86/X86ISelLowering.cpp
2012-10-15misched: ILP scheduler for experimental heuristics.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165950 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-12Merge commit '40573998821fde7ffeabe8507f4c9e8c7cf762f6'Derek Schuff
Conflicts: include/llvm/MC/MCAssembler.h lib/Target/ARM/ARMISelLowering.cpp lib/Target/X86/X86TargetMachine.h tools/llc/llc.cpp
2012-10-11Merge commit '2fa8af224ea026f9432e833fd6f42a216423a010'Derek Schuff
Conflicts: lib/ExecutionEngine/JIT/JITEmitter.cpp lib/MC/MCELFStreamer.cpp lib/Target/ARM/ARMAsmPrinter.h lib/Target/X86/X86RegisterInfo.td lib/Target/X86/X86TargetMachine.cpp tools/llc/llc.cpp
2012-10-11Remove unnecessary classof()'sSean Silva
isa<> et al. automatically infer when the cast is an upcast (including a self-cast), so these are no longer necessary. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165767 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-11Change MachineInstrBuilder::addDisp to copy over target flags by default.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165677 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10Add a new interface to allow IR-level passes to access codegen-specific ↵Nadav Rotem
information. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165665 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10misched: Use the TargetSchedModel interface wherever possible.Andrew Trick
Allows the new machine model to be used for NumMicroOps and OutputLatency. Allows the HazardRecognizer to be disabled along with itineraries. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165603 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-09misched: Add computeInstrLatency to TargetSchedModel.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165566 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-09misched: Doxument the TargetSchedule API.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165565 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-09misched: Allow flags to disable hasInstrSchedModel/hasInstrItineraries for ↵Andrew Trick
external users of TargetSchedule. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165564 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-09misched: Remove LoopDependencies heuristic.Andrew Trick
This wasn't contributing anything significant to postRA heuristics except compile time (by my measurements) and will be replaced by a more general heuristic for cross-region dependencies within the scheduler itself. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165563 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-09Add in some interfaces that will allow easier access to the pointer address ↵Micah Villmow
space. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165554 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-08misched: remove forceUnitLatencies. Defaults are handled by the default ↵Andrew Trick
SchedModel git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165417 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-08Move TargetData to DataLayout.Micah Villmow
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165402 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-07Remove unused MachineInstr constructors that don't take a DebugLoc argument.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165382 91177308-0d34-0410-b5e6-96231b3b80d8
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